3D Memory Array Strings With Jogged Through-Array Vias
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Solution Overview
Problem
Current memory array technologies face challenges in efficiently forming memory arrays with strings of memory cells, particularly in the integration of conductive and insulative tiers, and the formation of through-array-vias, which affects the electrical coupling and structural integrity of memory cells.
Innovation Solution
The method involves forming a stack with alternating conductive and insulative tiers, where partially-sacrificial plugs and insulative rings are used to create channel-material strings that electrically couple with conductor material, and through-array-vias are formed to extend through these tiers, enabling efficient electrical access and structural stability of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory array formation methods are used, then manufacturing simplicity is maintained, but electrical coupling and structural integrity of memory cells deteriorate
Solution Approach 1:
The memory array is divided into multiple strings of memory cells, with each string containing multiple memory cells arranged in series. This segmentation allows for better electrical coupling within each string while maintaining overall array integrity. The conductive and insulative tiers are also segmented into alternating layers, enabling precise control over electrical pathways and improving structural organization.
Solution Approach 2:
The patent transitions from planar memory array formation to three-dimensional stacked structures with alternating conductive and insulative tiers. This dimensional change enables vertical integration of memory cells in strings, improving electrical coupling through direct vertical connections while maintaining structural integrity through the layered architecture. The through-array-vias extend vertically through multiple tiers to establish electrical access.
2Ease of operation
If through-array-vias are formed to extend through conductive and insulative tiers, then electrical access is improved, but manufacturing complexity increases
Solution Approach 1:
The method forms preliminary openings in the insulative tiers before completing the through-array-via formation. These preliminary openings guide the subsequent via formation process, ensuring precise alignment and reducing manufacturing complexity. The alternating conductive and insulative tiers are prepared in advance with designated via locations, making the through-array-via formation more straightforward and controllable.
Solution Approach 2:
The insulative tiers serve as intermediaries between the conductive tiers, providing electrical isolation while allowing through-array-vias to pass through. This intermediary structure enables clean separation of electrical pathways, improving electrical access control while simplifying the via formation process by providing defined routes through the array.
3Stability of the object's composition
If alternating conductive and insulative tiers are formed, then structural integrity is improved, but device complexity increases
Solution Approach 1:
The conductive and insulative tiers are merged into a single integrated stacked structure, where alternating layers provide both electrical functionality and structural support. This merging creates a unified architecture that simultaneously achieves structural integrity and electrical performance, rather than treating them as separate concerns. The alternating pattern is built in a single fabrication sequence, reducing overall device complexity.
Solution Approach 2:
The alternating conductive and insulative tiers serve multiple functions simultaneously: the conductive tiers provide electrical pathways while the insulative tiers provide both electrical isolation and structural support. This multi-functionality reduces the need for additional dedicated structural layers, simplifying the overall device architecture while maintaining structural integrity.
Data Source
AI summary
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAVs comprises an upper portion directly above and joined with a lower portion. The individual TAVs in a vertical cross-section comprises at least one external upper jog surface. The individual TAVs comprise at least one external lower jog surface in the conductor tier in the vertical cross-section and that is below the upper jog surface. Other embodiments, including method, are disclosed.