Memory Array Layout Asymmetry for Reverse Engineering Resistance
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Solution Overview
Problem
The existing electrical fuses in integrated circuits (ICs) are vulnerable to reverse engineering, which compromises the security of proprietary information and data stored in one-time programmable memory elements, as the resistance changes during programming can be reverse-engineered, exposing manufacturer codes and information.
Innovation Solution
A layout method for forming a memory array with scrambled cut layers on control electrodes, which irregularly distribute the storage cells, preventing the identification of proprietary information through reverse engineering, by cutting polysilicon lines to create non-consecutive and irregular patterns such as Zigzag or U-shape arrangements, thereby enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical fuses are used to store permanent information in ICs, then non-volatile memory functionality is achieved, but security against reverse engineering is compromised
Solution Approach 1:
The patent applies asymmetry by implementing an irregular memory array layout where storage cells are deliberately positioned in non-uniform patterns. Control electrodes are connected to storage cells in an asymmetric configuration rather than a regular grid, making it difficult for reverse engineers to predict or systematically analyze the memory structure and extract proprietary information.
Solution Approach 2:
The patent introduces dimensional complexity by arranging storage cells and control electrodes in a multi-dimensional irregular pattern. Instead of a simple two-dimensional grid, the memory array utilizes complex spatial relationships across multiple dimensions, including irregular row and column connections, making reverse engineering significantly more difficult while maintaining full memory functionality.
2Ease of manufacture
If regular memory array layout is used, then manufacturing simplicity is maintained, but security against reverse engineering is reduced
Solution Approach 1:
The patent implements asymmetry in the memory array layout by deliberately avoiding regular, uniform patterns. Storage cells are positioned irregularly, and control electrodes are connected in non-standard configurations, creating an asymmetric structure that prevents systematic reverse engineering while remaining manufacturable using standard semiconductor fabrication processes.
Solution Approach 2:
The patent changes the spatial parameters of the memory array layout by varying cell positions, row lengths, column connections, and electrode placements. These parameter variations create an irregular pattern that enhances security against reverse engineering while being compatible with existing manufacturing capabilities.
3Object-affected harmful factors
If storage cells are irregularly distributed, then security against reverse engineering is enhanced, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple independent segments or blocks, each with its own irregular layout characteristics. This segmentation allows the complex irregular pattern to be managed as separate units during manufacturing and testing, reducing the practical impact of the increased complexity while maintaining the security benefits of the irregular overall structure.
Solution Approach 2:
The patent manages complexity by systematically varying specific parameters such as cell position coordinates, row and column connection patterns, and electrode placement rules. These controlled parameter changes create the desired irregularity for security while maintaining enough structure for manufacturability, balancing security enhancement with device complexity.
Data Source
AI summary
A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.