3D Memory Array Channel Doping via Etched Liner Void Spaces
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Solution Overview
Problem
Current methods for forming memory arrays, such as NAND architecture, face challenges in efficiently integrating vertically-stacked memory cells with effective gate structures and peripheral control circuitry, particularly in achieving optimal conductivity and isolation between memory blocks.
Innovation Solution
The method involves forming vertically-extending channel-material strings within a stack of alternating conductive and insulative tiers, with sacrificial pillars and liners used to create void-spaces for improved conductivity and dopant diffusion, and conductively-doped semiconductive material is formed to enhance channel material conductivity, while maintaining lateral isolation between memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If vertically-stacked memory cells are integrated with peripheral control circuitry, then memory array functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The memory array is divided into multiple memory blocks (first memory block, second memory block, etc.) with dedicated control circuitry for each block. This segmentation allows independent control and simplifies the overall manufacturing process by enabling modular fabrication approaches.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional vertically-stacked memory cells. Multiple tiers of memory cells are stacked above substrate circuitry, utilizing the vertical dimension to increase storage capacity without expanding the footprint, thereby improving functionality while managing manufacturing complexity through established 3D fabrication techniques.
2Reliability
If dopant diffusion is enhanced in channel material, then conductivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Sacrificial pillars are formed within the channel material before the dopant diffusion process. These pillars serve as pre-positioned diffusion barriers that define precise diffusion regions. The sacrificial material is later removed to create void spaces, having already established the boundaries for controlled dopant diffusion, thereby improving conductivity while maintaining manufacturing precision.
Solution Approach 2:
The sacrificial pillars act as intermediary structures during the dopant diffusion process. They temporarily occupy the space where void spaces will eventually be formed, allowing dopants to diffuse uniformly up to the pillar boundaries. This intermediary approach ensures precise diffusion control without requiring direct patterning of the diffusion regions.
3Reliability
If void-spaces are formed for dopant diffusion, then conductivity enhancement is improved, but manufacturing complexity increases
Solution Approach 1:
Sacrificial pillars are formed in advance within the channel material at the locations where void spaces are needed. These pillars guide the subsequent isotropic etching process, ensuring that void spaces are created with precise dimensions and positioning. The preliminary placement of sacrificial material simplifies the overall process by providing a self-aligned template for void space formation.
Solution Approach 2:
The sacrificial pillars automatically define the boundaries and dimensions of the void spaces through their own geometry. When the sacrificial material is removed via isotropic etching, the void spaces self-form with precise dimensions without requiring additional patterning steps. This self-service approach reduces manufacturing complexity while achieving the desired conductivity enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of memory arrays with enhanced conductivity and isolation, leading to improved performance and reliability of memory cells, particularly in vertically-stacked configurations.
Implementation Method 1
The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces
Implementation Method 2
The liners are isotropically etched to form void-spaces in the one second tier above the one first tier
Data Source
AI summary
A liner is formed laterally-outside of individual channel-material strings in one of first tiers and in one of second tiers. The liners are isotropically etched to form void-spaces in the one second tier above the one first tier. Individual of the void-spaces are laterally-between the individual channel-material strings and the second-tier material in the one second tier. Conductively-doped semiconductive material is formed against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier. The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces.