Memory Array Local Voltage Source Pre-Charge Disturbance
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Solution Overview
Problem
In memory arrays, half-selected memory cells experience voltage disturbance during read and write cycles due to pre-charging of bit lines and bit line bars to a working voltage, which affects data integrity and efficiency.
Innovation Solution
The implementation of a local voltage source comprising NMOS transistors to pre-charge bit lines and bit line bars with a voltage lower than the working voltage for unselected columns, reducing voltage division and disturbance, while maintaining the read speed and write ability of selected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit lines and bit line bars are pre-charged to working voltage before read cycle, then read speed is improved, but voltage disturbance in half-selected memory cells increases
Solution Approach 1:
The patent applies local quality by providing different pre-charge voltages to different columns of memory cells. Selected columns receive full working voltage for fast read access, while unselected columns receive reduced voltage to minimize disturbance in half-selected cells. This spatial differentiation of voltage levels resolves the contradiction between read speed and disturbance.
Solution Approach 2:
The patent segments the memory array into selected and unselected columns based on word line activation status. By segmenting the pre-charge operation into two distinct voltage levels corresponding to these segments, the system optimizes read performance in selected columns while protecting unselected columns from excessive disturbance.
2Ease of operation
If bit lines and bit line bars are pre-charged to working voltage before write cycle, then write ability is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by providing different pre-charge voltages to different columns of memory cells. Selected columns receive full working voltage for successful write operation, while unselected columns receive reduced voltage to minimize power consumption. This spatial differentiation of voltage levels resolves the contradiction between write ability and power consumption.
Solution Approach 2:
The patent applies partial action by providing only the necessary voltage level to each column segment. Unselected columns receive partial pre-charge (reduced voltage) instead of full pre-charge, which is sufficient for their operation but avoids excessive power consumption. Selected columns receive full pre-charge when needed for write operations.
3Device complexity
If same pre-charge voltage is applied to all columns, then circuit complexity is reduced, but disturbance in half-selected cells increases
Solution Approach 1:
The patent introduces dynamic voltage selection based on column selection status. The pre-charge circuit dynamically adjusts the voltage level supplied to different column segments according to the word line activation state. This dynamic adaptation allows the system to reduce disturbance in unselected columns while maintaining simple circuit architecture through controlled voltage differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes disturbance in half-selected memory cells during read and write cycles, reduces pre-charge time, and lowers power consumption by using a lower voltage for unselected columns, thereby enhancing data integrity and operational efficiency.
Implementation Method 1
the bit line BL and the bit line bar BLB are pre-charged to a working voltage VDD, which causes higher divided voltage (Disturb weak point in FIG. 2) at node Na or node Nb
Data Source
AI summary
A memory array includes a plurality of columns of memory cells and each column of memory cells of the memory array is coupled to a local voltage source, a bit line, and a bit line bar. Provide a working voltage to pre-charge the bit line and the bit line bar of the column of memory cells when a memory cell of the column of memory cells is selected to be read, and meanwhile use local voltage sources coupled to remaining columns of memory cells of the memory array to provide high voltages lower than the working voltage to pre-charge bit lines and bit line bars of the remaining columns of memory cells.