Memory Array Defect Detection via Program Loop Delta
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Solution Overview
Problem
Existing memory devices face challenges in detecting defects, such as silent read failures, which can result in data loss, particularly due to defects like short circuits between word lines or leaky select gate transistors, and current detection techniques are inefficient or incur performance penalties.
Innovation Solution
A method to detect defective memory arrays by comparing the programming speed of memory cells connected to different word lines, specifically through the program loop delta, which represents the difference in the number of program-verify loops required for each word line to complete programming, allowing for identification of defects without the need for post-write read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If post-write read operations are used to detect defects, then detection accuracy is improved, but device complexity and performance penalties increase
Solution Approach 1:
The patent extracts the defect detection function from the complex post-write read operation sequence and implements it through a simplified program loop delta comparison mechanism. By monitoring only the difference in program loop counts between adjacent word lines during normal programming, the system achieves defect detection without requiring separate read verification operations, thus reducing operational complexity while maintaining detection capability.
Solution Approach 2:
The programming operation itself serves the dual purpose of data programming and defect detection. The program loop delta metric is automatically generated during normal programming without requiring additional detection operations. This self-service approach eliminates the need for separate detection mechanisms and reduces overall system complexity.
2Reliability
If traditional defect detection methods are implemented, then defect identification capability is improved, but productivity and programming speed deteriorate
Solution Approach 1:
The patent merges the defect detection function with the normal programming operation by using the same program-verify loop structure for both purposes. The program loop delta comparison is performed automatically during programming without requiring separate detection passes, thus maintaining programming speed while enabling continuous defect monitoring throughout the programming process.
Solution Approach 2:
The defect detection mechanism operates continuously during normal programming operations rather than requiring intermittent or post-processing detection steps. The program loop delta is calculated and compared in real-time during each programming cycle, ensuring continuous defect identification capability without interrupting the programming workflow.
3Reliability
If comprehensive defect detection is performed, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent performs defect detection during the programming process itself rather than as a subsequent separate operation. By detecting defects while programming is occurring, the system eliminates the time loss associated with post-programming detection operations, while still achieving comprehensive defect coverage through the program loop delta comparison mechanism.
Data Source
AI summary
Apparatuses and techniques are described for detecting a defect in a memory cell array during program operations. A defect can be detected by comparing the programming speed of memory cells connected to different word lines, for one or more programmed data states. The comparison can involve adjacent word lines in a block, or word lines in different blocks and planes. The comparison involves comparing two word lines in terms of a number of program-verify loops used to reach the programmed data states or to transition between programmed data states. If a program loop delta is not within an allowable range for one or more of the programmed data states, it can be concluded that a defect is present. The block which has the slower programming word line can be identified as a bad block.