Memory Array MAC Circuit Using Multi-Bit Capacitor Weights
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Solution Overview
Problem
Conventional in-memory MAC operation devices deform existing memory structures, leading to deteriorated memory performance, increased area occupation, and power consumption, and are limited to 1-bit data or weights, restricting data accuracy.
Innovation Solution
A semiconductor device with a memory cell array and an operation circuit that performs MAC operations using multi-bit data, where memory cells store multiple bits of weights and sequentially provide them to the operation circuit for processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional in-memory MAC operation device structure is used, then MAC operation capability is provided, but memory performance deteriorates and area occupation increases
Solution Approach 1:
The patent segments the weight data into multiple bits stored in separate memory cells within each memory cell array unit. Each memory cell stores one bit of multi-bit weight data, and the bits are sequentially read and processed. This segmentation allows MAC operations to be performed using standard memory structures without deformation, maintaining memory performance while enabling MAC functionality.
2Adaptability or versatility
If conventional in-memory MAC operation device structure is used, then MAC operation capability is provided, but area occupation increases
Solution Approach 1:
The patent makes the memory cell array units universal by enabling them to perform both standard memory read operations and MAC operations using the same hardware structure. The operation circuit can selectively perform either function based on control signals, eliminating the need for separate dedicated MAC operation circuits and reducing overall area occupation.
3Device complexity
If 1-bit data or weights are used, then device structure is simplified, but data accuracy is limited
Solution Approach 1:
The patent changes the parameter of data representation from 1-bit to multi-bit weights stored in memory cells. Each memory cell stores one bit of multi-bit weight data, and multiple memory cells work together to represent complete multi-bit weights. This parameter change enables higher data accuracy while maintaining the simplicity of individual memory cell structures.
4Measurement precision
If multi-bit data is used in MAC operations, then data accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where the memory cell array units themselves perform the MAC operations using their stored weight data and input data from bit lines. The operation circuit within each memory cell array unit handles the multiplication and accumulation internally, eliminating the need for complex external MAC operation circuits and reducing overall device complexity while maintaining multi-bit data accuracy.
Data Source
AI summary
A semiconductor device includes a memory cell array including a plurality of memory cells coupled between a multiplicity of word lines and one or more bit lines; and an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data, wherein a plurality of memory cells coupled to a bit line store a plurality of bits included in a corresponding one of the one or more first multi-bit data, and wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit.