On-Chip Memory Array Comparison for Data Match Verification
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Solution Overview
Problem
In semiconductor memory systems, determining a match between data values stored by multiple arrays is crucial for ensuring accurate execution of instructions, particularly in critical applications like autonomous systems, where errors can lead to safety and performance issues.
Innovation Solution
The implementation of comparator circuitry on a single memory chip to compare data values stored by two arrays and output the correct data values based on a match determination, with the ability to notify of no match for failover functionality, enhancing data integrity and system reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data values are stored in multiple arrays and compared using external processing resources, then data integrity can be verified, but the complexity of the system increases and access time increases due to bus communication
Solution Approach 1:
The patent combines the comparator circuitry with the memory arrays on the same memory chip, merging previously separate functions (storage and comparison) into an integrated unit. This reduces system complexity by eliminating external processing resources and bus communication while maintaining data integrity verification capability through on-chip comparison circuits that directly compare data values from multiple arrays.
Solution Approach 2:
The patent introduces an intermediary comparator component that sits between the memory arrays and external processing resources. This intermediary performs the comparison function locally on the memory chip, acting as a mediator that verifies data integrity before data leaves the memory device, thereby reducing the need for complex external verification systems.
2Adaptability or versatility
If data values are accessed via bus between memory array and external processor, then processing flexibility is maintained, but access time increases and productivity decreases
Solution Approach 1:
The patent segments the memory system into independent functional blocks on the same chip, with each array and the comparator operating as separate but integrated units. This segmentation allows parallel operation of multiple arrays with the shared comparator, enabling simultaneous data retrieval and comparison operations that improve productivity while maintaining processing flexibility through selective array access.
3Speed
If comparator circuitry is integrated on the memory chip, then data access speed improves, but manufacturing complexity increases
Solution Approach 1:
The patent designs the comparator circuitry as a universal component that can compare data values from any combination of the multiple memory arrays. This multi-functional comparator serves all arrays simultaneously, reducing the need for separate comparison circuits for each array pair. The universal design simplifies manufacturing by using a single standardized comparator block that handles all comparison operations across different array configurations.
Data Source
AI summary
Apparatuses, systems, and methods related to determination of a match between data values stored by several arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by two arrays selected from the plurality to determine whether there is a match between the data values stored by the two arrays. The apparatus further includes an output component configured to output data values of one of the two arrays responsive to determination of the match between the data values stored by the two arrays.