Memory Array Column-Plane Layout for Single-Pass Metadata ECC Access
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Solution Overview
Problem
Existing memory devices face limitations in retrieving error correction information and metadata alongside data without impacting performance, often requiring multiple access passes, which increases latency and power consumption.
Innovation Solution
A semiconductor memory device architecture that stores metadata and error correction parity bits in both data column planes and an extra column plane, allowing for single-pass access of codewords, including data, metadata, and parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metadata and error correction information are stored in the memory array alongside data, then information storage capability is improved, but access latency increases due to requiring multiple access passes
Solution Approach 1:
The memory array is segmented into data regions and metadata regions, with metadata stored in dedicated regions (e.g., region 115 in FIG. 1) separate from primary data regions. This segmentation allows independent access to metadata without requiring full array access, reducing latency when retrieving metadata alongside data.
Solution Approach 2:
The patent introduces an additional spatial dimension by implementing multiple column planes (first set and second set of column planes) where metadata can be stored in column planes distinct from those storing data. This dimensional separation enables simultaneous or near-simultaneous access to both data and metadata through parallel column plane access, effectively reducing access latency.
2Reliability
If multiple access passes are used to retrieve data and error correction information, then data integrity is improved, but power consumption increases
Solution Approach 1:
The system performs preliminary actions by pre-fetching and storing error correction code (ECC) data and metadata in dedicated buffer memory regions before they are needed for data verification. This preliminary positioning of correction information allows single-pass access to both data and ECC, eliminating the need for repeated access passes and reducing power consumption while maintaining data integrity verification.
Solution Approach 2:
The patent merges the retrieval of data, metadata, and error correction information into a single unified access operation. By organizing memory structures to allow simultaneous access to all three information types through a single access pass, the system eliminates multiple separate access passes, thereby reducing power consumption while ensuring data integrity through combined verification.
3Device complexity
If error correction code data is stored in the same memory array as primary data, then device complexity is reduced, but access speed decreases due to sequential retrieval requirements
Solution Approach 1:
The memory array is segmented into distinct regions for primary data and ECC data, with separate column planes dedicated to each type. This segmentation allows parallel access paths where data and ECC can be retrieved simultaneously through different column plane sets, maintaining low device complexity while improving access speed through spatial separation.
Solution Approach 2:
The patent introduces intermediary buffer memory structures and control logic that mediate between the memory array and external interfaces. These intermediaries enable the system to present unified access to data and ECC information while internally managing parallel retrieval paths, effectively increasing access speed without significantly increasing overall device complexity.
Data Source
AI summary
Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.