Memory Module Bank Array Layout for In-Place Metadata Storage
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Solution Overview
Problem
Existing memory technologies face inefficiencies in handling metadata, leading to increased chip size, power consumption, and reduced bus efficiency due to separate memory cells or separate read commands for normal data and metadata.
Innovation Solution
A memory device with a bank array divided into regions for normal data and metadata, allowing simultaneous read/write operations using different column addresses in different modes, without additional memory cells or read commands, thus maintaining storage capacity and bus efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate memory cells are used for metadata storage, then metadata can be stored, but chip size increases
Solution Approach 1:
The patent applies multi-functionality by enabling the bank array to serve dual purposes: storing normal data in the first region and storing metadata in the second region. The same memory structure is used for both data types, eliminating the need for separate dedicated metadata storage cells and thus avoiding chip size increase while maintaining metadata storage capability.
Solution Approach 2:
The bank array is segmented into two distinct regions: a first region for normal data and a second region for metadata. This segmentation allows independent management and addressing of metadata without requiring additional memory cells, as the metadata region is a designated portion of the existing bank array structure.
2Adaptability or versatility
If separate read commands are used for metadata, then metadata can be read, but bus efficiency decreases
Solution Approach 1:
The patent merges the metadata read operation with the normal data read operation by using a unified read command structure. The column decoder simultaneously activates column selection lines in both the first region (for normal data) and the second region (for metadata) based on column addresses, allowing both types of data to be read through the same bus interface without requiring separate commands, thereby maintaining bus efficiency.
3Adaptability or versatility
If additional memory cells are added for metadata, then metadata storage is enabled, but power consumption increases
Solution Approach 1:
The patent uses the existing bank array structure for both normal data and metadata storage, avoiding the addition of new memory cells. Since no additional cells are added, the power consumption remains unchanged while metadata storage capability is enabled through the second region of the existing array.
4Productivity
If the bank array is divided into regions for normal data and metadata, then metadata can be stored efficiently, but device complexity increases
Solution Approach 1:
The bank array is divided into a first region and a second region with clear functional separation. The column decoder is enhanced to handle column addresses that can selectively activate column selection lines in either the first region, the second region, or both simultaneously. This segmented approach enables efficient metadata handling while keeping the structural complexity manageable through systematic region management.
Data Source
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AI summary
Disclosed is a memory device which includes a bank array including a plurality of memory cells, a row decoder connected to the bank array through a plurality of word lines, and a column decoder connected to the bank array through a plurality of column selection lines. The bank array includes a first region and a second region different from the first region. The memory device is configured to operate in a first mode, in which the first region stores normal data and the second region stores metadata based on a first number of column addresses, respectively. The memory device is configured to operate in a second mode, in which the first region and the second region store normal data based on a second number of column addresses. The second number is greater than the first number.