Memory Array Layout With Mixed Bit Storage for Higher Density
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Solution Overview
Problem
Existing memory systems face challenges in achieving better memory performance, capacity, and power efficiency due to the slowing pace of Moore's Law, leading to reduced spatial efficiency and density.
Innovation Solution
The proposed memory structure incorporates two types of structures for storing bits: single-memory-element structures for most significant bits (MSBs) and multiple-memory-element structures for least significant bits (LSBs), optimizing memory-element-to-transistor ratio to enhance spatial efficiency and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory structures are used, then memory capacity can be maintained, but spatial efficiency and density decrease due to the slowing pace of Moore's Law
Solution Approach 1:
The patent segments the memory array into distinct regions: first memory structures with one memory element per transistor, and second memory structures with multiple memory elements per transistor. This segmentation allows different spatial efficiencies in different regions, optimizing overall density while maintaining adequate capacity.
Solution Approach 2:
The patent transitions from a uniform two-dimensional memory layout to a heterogeneous structure that effectively utilizes vertical dimension by stacking multiple memory elements in the second memory structures, thereby increasing spatial efficiency and density without proportionally increasing footprint area.
2Area of stationary object
If memory-element-to-transistor ratio is increased to enhance density, then spatial efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory array into first and second memory structures with different memory-element-to-transistor ratios. The first memory structures use a 1:1 ratio for simplicity, while the second memory structures use higher ratios for density. This segmentation manages manufacturing complexity by isolating the more complex structures to specific regions.
Solution Approach 2:
Different regions of the memory array are assigned different memory-element-to-transistor ratios based on local requirements. The second memory structures with higher ratios are placed in regions where density is prioritized, while the first memory structures with 1:1 ratio are used where manufacturing simplicity is more important, achieving local optimization.
Data Source
AI summary
In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.