Memory Array Logic Model Verification via Segmentation
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Solution Overview
Problem
Current methods for emulating processor cores on Field Programmable Gate Arrays (FPGAs) face challenges in implementing full custom arrays and register files, particularly in generating and verifying technology-specific and technology-independent logic models for memory arrays, which are essential for efficient FPGA emulation and production.
Innovation Solution
A computer-implemented method that generates and verifies technology-specific and technology-independent logic models of memory arrays by accessing parameters and constraints, creating a technology-independent model, and verifying equivalence on a sequential logic basis, using VHDL for description and generics to define implementation styles, enabling faster verification and production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If technology-specific logic models are used for FPGA emulation, then implementation accuracy is improved, but device complexity and verification time increase
Solution Approach 1:
The patent divides the verification process into two independent models: a technology-independent logic model (TILM) that captures functional behavior without technology-specific details, and a technology-specific logic model (TSLM) that implements actual FPGA architecture. This segmentation allows verification of critical functional logic without being burdened by technology-specific complexity, resolving the contradiction between accuracy and complexity.
Solution Approach 2:
The technology-independent logic model serves as an intermediary between the design specification and the technology-specific implementation. It acts as a mediator that verifies functional correctness without incorporating FPGA-specific details, thereby maintaining verification simplicity while ensuring accurate functional behavior before proceeding to technology-specific implementation.
2Manufacturing precision
If technology-specific logic models are used for verification, then implementation fidelity is improved, but verification time increases
Solution Approach 1:
The patent performs preliminary verification using the technology-independent logic model before proceeding to technology-specific implementation. By verifying functional correctness at the TILM level first, the method eliminates the need for extensive re-verification at the TSLM level, significantly reducing total verification time while maintaining implementation fidelity through the subsequent technology-specific model generation.
3Productivity
If full custom arrays are implemented on FPGA, then processing capability is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent creates a technology-independent copy of the logic model that reproduces the functional behavior of custom arrays without requiring actual custom array implementation on FPGA. This copied model can be verified and validated much more easily, and only after successful verification is the technology-specific implementation generated, thereby improving ease of manufacture while maintaining processing capability.
4Productivity
If technology-independent models are used for equivalence checking, then verification speed is improved, but measurement precision may deteriorate
Solution Approach 1:
The patent applies local quality by making the technology-independent logic model sufficiently detailed to capture all functional behavior relevant to equivalence checking, while deliberately excluding technology-specific implementation details. This selective level of detail provides the right balance: enough precision for accurate equivalence verification, but abstract enough to maintain high verification speed.
Data Source
AI summary
A computer implemented method for automated generation and verification of a technology specific logic model and a technology independent logic model of a memory array, the method at least comprising: having a first set of parameters; having a set of constraints, creating a second set of parameters; generating the technology independent model of the memory array wherein the second set of parameters and the set of constraints are used; generating the technology specific model of the memory array wherein the first set of parameters and the set of constraints are used; verifying the technology independent model and the technology specific model for equivalence on a sequential logic basis.