Memory Array Error Correction Using Multi-Directional Checks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current error correction methods in programmable logic devices (PLDs) are inadequate for detecting and correcting multiple errors in memory arrays, particularly in small dimensions where cosmic rays can upset multiple memory cells, leading to increased errors and system downtime during real-time operations.
Innovation Solution
A method that involves reading back data from the memory array, performing error checks in multiple directions using techniques like parity checks and cyclic redundancy checks, and selectively changing cell states to correct errors based on the detected errors in intersecting rows and columns, allowing for precise location and correction of errors in larger error matrices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-direction error correction methods are used, then single errors can be corrected, but multiple errors caused by cosmic rays cannot be detected or corrected
Solution Approach 1:
The patent extends error detection from single-direction (row-only or column-only) checks to multi-directional checks by adding diagonal checking dimensions. This allows the system to detect and correct multiple errors that occur simultaneously in different spatial orientations within the memory array, resolving the limitation of conventional single-direction methods.
Solution Approach 2:
The memory array is divided into multiple checkable dimensions (rows, columns, and diagonals), with independent parity bits allocated to each dimension. This segmentation allows each direction to be checked independently, enabling the system to identify and correct multiple errors that would be indistinguishable in a single-direction approach.
2Measurement precision
If multiple error detection methods are implemented, then detection accuracy improves, but system complexity increases
Solution Approach 1:
By adding diagonal checking dimensions to the existing row and column checking structure, the patent achieves higher error detection accuracy without fundamentally changing the underlying error correction code structure. The additional dimensional checks provide more error location information while maintaining compatibility with existing ECC mechanisms.
Solution Approach 2:
The parity bit structure is designed to serve multiple functions simultaneously: row parity bits detect row errors, column parity bits detect column errors, and diagonal parity bits detect diagonal errors. This multi-functionality allows a single unified system to handle multiple error types and orientations without requiring separate dedicated systems for each error mode.
3Reliability
If comprehensive error checking is performed in all directions, then all errors can be detected, but processing time increases
Solution Approach 1:
Parity bits for all dimensions (rows, columns, and diagonals) are pre-calculated and stored alongside the data bits during the write operation. This preliminary preparation eliminates the need for complex real-time calculations during error checking, allowing the system to quickly verify errors by simply comparing stored parity bits with newly calculated ones, thus reducing processing time while maintaining comprehensive detection capability.
Data Source
AI summary
A method of correcting errors stored in a memory array is disclosed. According to various embodiments of the invention, the method comprises the steps of storing data in the memory array; reading back the data stored in the memory array; performing a check for errors on each frame of data in a first direction; and performing a check for errors in a second direction. The step of performing a check for errors may include a parity check or a cyclical redundancy check. Depending upon the number of errors detected in intersecting rows and columns, the state of cells of the memory array are selectively changed.