Memory Array Noise Reduction via Selective Word Line Driving
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Solution Overview
Problem
Memory arrays face increased noise issues due to parasitic capacitance, which degrades signal quality and can lead to read errors, especially in smaller feature sizes and cross-point configurations, where signal-to-noise ratios are compromised.
Innovation Solution
The implementation of a memory circuit architecture that selectively drives word lines to positive or negative voltages based on column address signals, isolating bit lines to prevent noise coupling and maintaining a stable precharge voltage, thereby maximizing the signal-to-noise ratio and reducing array noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is decreased to increase memory density, then memory capacity increases, but parasitic capacitance increases causing array noise to worsen
Solution Approach 1:
The memory array is divided into multiple independent sub-arrays, each with its own sense amplifiers. This segmentation isolates noise within each sub-array, preventing noise propagation across the entire array, thereby maintaining signal integrity while achieving high density through the combined capacity of multiple sub-arrays.
Solution Approach 2:
Different regions of the memory array are configured with different architectures - cross-point configuration in high-density regions and folded bit line configuration in regions requiring lower noise. This allows optimization of local noise characteristics while maintaining overall high capacity.
2Quantity of substance
If cross-point configuration is used to increase density, then memory capacity increases, but signal-to-noise ratio deteriorates due to increased parasitic capacitance coupling
Solution Approach 1:
The cross-point memory array is divided into multiple independent sub-arrays, each processed by dedicated sense amplifiers. This segmentation prevents noise coupling between sub-arrays, maintaining high signal-to-noise ratio while achieving high capacity through the aggregation of multiple sub-arrays.
Solution Approach 2:
Isolation structures are introduced between adjacent bit lines and word lines in the cross-point configuration. These intermediaries reduce parasitic capacitance coupling, thereby improving signal-to-noise ratio while preserving the high-density cross-point architecture.
3Quantity of substance
If bit lines are placed in close proximity to increase density, then memory capacity increases, but noise coupling between adjacent bit lines increases
Solution Approach 1:
The memory array is segmented into multiple sub-arrays with dedicated sense amplifiers for each sub-array. This segmentation isolates noise generated by bit line transitions within each sub-array, preventing noise coupling to other sub-arrays, thereby maintaining high capacity while reducing overall noise coupling.
Solution Approach 2:
Different regions of the array use different bit line configurations - folded bit line architecture in regions where noise coupling must be minimized, and cross-point configuration in regions where density is prioritized. This local differentiation optimizes the balance between capacity and noise coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the signal-to-noise ratio, allowing for faster sensing and reduced read errors by minimizing noise interference between bit lines, particularly at the ends of the memory array, where bit line capacitance is lower.
Implementation Method 1
The signal transitions are often coupled to the data signal through parasitic capacitance due to the close proximity of the interfering signal lines.
Data Source
AI summary
A method of operating a memory circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The method includes selecting a word line (708) connected to a row of memory cells in response to a plurality of row address signals and selecting a plurality of columns (706,710) of memory cells in response to a plurality of column address signals. A first part (714) of the plurality of columns is selected in response to a first voltage applied to the selected word line. A second part (716) of the plurality of columns is selected in response to a second voltage applied to the selected word line.