Semiconductor Memory Cell Array Overlap for High-Density Integration
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing data storage capacity and reliability, particularly in achieving high integration and efficient data storage in electronic systems.
Innovation Solution
A semiconductor memory device design featuring a substrate with pass transistor regions and a cell array structure comprising vertically stacked conductive patterns with stepwise structures, where the cell array structure overlaps pass transistor regions, enhancing integration and data storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensionally arranged memory cells are used, then the device structure is simple, but the data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertically stacked conductive patterns. Multiple memory layers are stacked vertically on the substrate, enabling data storage in the vertical dimension while maintaining planar footprint, thus significantly increasing storage capacity without proportionally increasing device area
Solution Approach 2:
The patent implements nested structures where multiple conductive patterns and memory layers are stacked within each other vertically. Each layer contains conductive patterns that are nested within the vertical space of the device, with connection regions overlapping between layers to create a compact three-dimensional memory structure
2Quantity of substance
If three-dimensionally arranged memory cells are used, then the data storage capacity increases, but the manufacturing precision requirement increases
Solution Approach 1:
The patent forms connection regions in advance on the substrate before stacking the vertically stacked conductive patterns. These connection regions are pre-positioned to ensure accurate alignment with the pass transistor regions and subsequent layers, reducing the complexity of alignment during the stacking process
Solution Approach 2:
The patent merges the connection regions with the pass transistor regions by making them overlap in the planar view. This integration reduces the number of separate alignment steps required, as the connection regions serve dual purposes: connecting vertical stacks and aligning with pass transistors in the same manufacturing step
3Device complexity
If connection regions are added to connect vertical stacks with pass transistors, then the integration is improved, but the device area increases
Solution Approach 1:
The patent resolves the area issue by moving connection functions to the vertical dimension. Connection regions are positioned at different vertical levels between the substrate and the top of vertically stacked conductive patterns, allowing electrical connection without requiring additional lateral space. This vertical stacking approach enables high integration while maintaining compact planar footprint
Data Source
AI summary
A semiconductor memory includes a substrate that includes pass transistor regions, a peripheral circuit structure that includes pass transistors on the pass transistor regions, and a cell array structure on the peripheral circuit structure, the cell array structure including a plurality of cell array regions and a plurality of connection regions that are alternately arranged along a first direction. The cell array structure includes a stack structure including conductive patterns vertically stacked and correspondingly connected to the pass transistors. The stack structure includes stepwise structures on the connection regions. The connection regions of the cell array structure correspondingly overlap the pass transistor regions of the peripheral circuit structure.