3D Memory Array Strings With Oxide-Protected Conductor Tiers
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Solution Overview
Problem
Current memory array fabrication methods face challenges in efficiently forming vertically-stacked memory cells with precise control over sacrificial materials and etching processes, which can lead to inefficiencies and potential etching of polysilicon-comprising upper conductor materials.
Innovation Solution
The method involves forming a conductor tier with conductively-doped polysilicon, creating a stack with alternating insulative and conductive tiers, and using oxidizing conditions to form silicon dioxide in trenches, followed by selective etching of sacrificial materials to form channel-material strings electrically coupled to the conductor tier, with intervening insulating material and side interfaces to enhance memory cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form vertically-stacked memory cells, then manufacturing process simplicity is maintained, but electrical connection reliability and structural integrity deteriorate
Solution Approach 1:
The patent applies preliminary action by forming conductor tiers and insulative tiers with sacrificial materials before forming the channel material strings. The conductor tiers are prepared in advance with oxidizing conditions applied to create silicon dioxide layers that protect against subsequent etching. This preliminary preparation ensures that when etching occurs later to create the vertical structures, the conductor materials are already protected and will maintain their structural integrity and electrical connection reliability.
Solution Approach 2:
The patent uses sacrificial materials as intermediaries during the fabrication process. These sacrificial materials are temporarily placed in the structure to define regions, then selectively removed through etching to create the desired vertical channel structures. The silicon dioxide formed on conductor tier surfaces acts as an intermediary protective layer that mediates between the etching process and the conductor materials, preventing unwanted etching while allowing the etch to proceed in other regions.
2Stability of the object's composition
If conventional fabrication methods are used to form vertically-stacked memory cells, then manufacturing simplicity is maintained, but structural integrity deteriorates
Solution Approach 1:
The patent applies preliminary action by forming conductor tiers and insulative tiers with sacrificial materials before forming the channel material strings. The conductor tiers are prepared in advance with oxidizing conditions applied to create silicon dioxide layers that protect against subsequent etching. This preliminary preparation ensures that when etching occurs later to create the vertical structures, the conductor materials are already protected and will maintain their structural integrity and electrical connection reliability.
Solution Approach 2:
The patent employs composite material structures by combining conductor materials (such as polysilicon or metal) with insulative materials (such as silicon dioxide or silicon nitride) in vertically-stacked tiers. This composite construction provides both structural integrity and electrical isolation. The oxidation of conductor tier surfaces creates a composite protective oxide layer that integrates with the underlying conductor material, enhancing overall structural stability during subsequent processing steps.
3Manufacturing precision
If etching is performed to create vertical structures, then memory cell formation is achieved, but conductor materials are damaged by etching agents
Solution Approach 1:
The patent applies preliminary anti-action by pre-treating the conductor tier surfaces with oxidizing conditions before the etching process. This creates a protective silicon dioxide layer on the conductor materials that acts as a barrier against etching agents. The oxidized surface resists the harmful effects of subsequent etching processes, preventing damage to the conductor materials while still allowing the etch to proceed in regions without this protective oxidation, thereby achieving precise vertical structure formation.
Solution Approach 2:
The patent converts the potential harm of etching agents into a benefit by using controlled oxidation first. The oxidation process, which might seem like an additional step, actually protects the conductor materials from etching damage. The silicon dioxide formed during oxidation serves as a mask or protective layer during etching, transforming what would be a harmful exposure to etchants into a protective mechanism that ensures manufacturing precision.
4Reliability
If gate-last or replacement-gate processing is employed, then electrical coupling is enhanced, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the conductor tiers and insulative tiers with all necessary conductive and insulative structures in place before forming the channel material strings. This preliminary arrangement of tiers allows for enhanced electrical coupling to be built into the structure itself, rather than requiring additional gate formation steps later. The conductor tiers are positioned and prepared in advance to provide optimal electrical pathways.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of robust memory arrays with improved etching control, protecting polysilicon and forming efficient channel-material strings and memory cells, enhancing the overall structure and functionality of the memory array.
Implementation Method 1
The polysilicon of the first sacrificial material and the conductively-doped polysilicon of the conductor tier are simultaneously exposed to oxidizing conditions to form silicon dioxide over sidewalls of the first trenches within the conductor tier
Data Source
AI summary
A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The channel material of individual of the channel-material strings is directly electrically coupled to the conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. The conductor material in the conductor tier comprises a pair of side interfaces that individually extend downwardly from a top of the conductor tier on one of opposing sides of the intervening material and individually extend longitudinally-along the immediately-laterally-adjacent memory blocks. The side interfaces have the conductor material laterally-over opposing sides thereof. Other embodiments, including method, are disclosed.