Memory Array Partitioning for Reliability and Speed Trade-offs

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Solution Overview

Problem

Memory devices face reliability degradation due to program-erase cycles, especially when storing different types of information, where critical data requires high reliability and low program speed, while less important data can tolerate lower reliability for faster write speeds.

Innovation Solution

A memory array is partitioned into multiple partitions with distinct attributes, such as reliability and program speed, using different error correcting codes and sense amplifier circuits, allowing for selective storage based on the type of information, with partitions configured during manufacture or dynamically by a host processor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single memory array stores all types of information, then memory capacity is maximized, but reliability deteriorates due to program-erase cycles degrading physical integrity

Engineering Contradiction:
Improvememory reliabilityVSAvoidprogram-erase cycle durability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory array is divided into multiple partitions (first partition, second partition, third partition) with different reliability characteristics. Each partition is optimized for specific storage needs, allowing critical data to be stored in high-reliability partitions while less critical data uses partitions tolerant of more program-erase cycles.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different partitions are assigned different error correcting codes (ECC) based on their reliability characteristics. High-reliability partitions use stronger ECC codes, while lower-reliability partitions use lighter ECC codes, optimizing the balance between reliability and write speed for each local region of the memory array.

Inventive Principle:
Principle #3Local quality

2Reliability

If error correcting codes are applied to all memory partitions, then read error rate decreases, but write speed deteriorates due to additional processing overhead

Engineering Contradiction:
Improveread error rateVSAvoidwrite speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

Different error correcting codes are applied to different partitions based on their reliability characteristics and access patterns. Critical data partitions use strong ECC codes for low read error rates, while less critical partitions use lighter ECC codes to maintain faster write speeds.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of applying maximum ECC protection to all data, the system applies ECC selectively and partially - using stronger ECC where needed (high-reliability partitions) and weaker or no ECC where acceptable (lower-reliability partitions), optimizing the balance between error protection and write performance.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10185622B2Memory device having address and command selectable capabilities
Publication Date: 2019.01.22 MICRON TECHNOLOGY INC
  • US10185622B2 patent drawing
  • US10185622B2 patent drawing
  • US10185622B2 patent drawing

AI summary

Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.