3D Memory Array Layout Using Dummy Arrays for Pattern Density Control

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Solution Overview

Problem

The existing 3D memory device fabrication processes face issues due to large discrepancies in pattern density between areas with and without memory arrays, leading to process contamination and failure in polishing processes.

Innovation Solution

Concurrently forming active and dummy memory arrays in adjacent areas on a substrate, using a stack of insulating and sacrificial layers, and etching trenches and holes to create conductive structures, followed by conformal deposition of metallic and semiconductor layers, thereby reducing process contamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If memory arrays are formed only in specific areas of the substrate, then the integration density is improved, but large discrepancies in pattern density occur between areas with and without memory arrays, leading to process contamination and polishing failures

Engineering Contradiction:
Improvepattern density consistencyVSAvoidprocess contamination
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent creates dummy memory arrays that are copies of the actual memory array structure but are non-functional. These dummy arrays are formed in areas where no active memory is needed, copying the same pattern density, layer structure, and fabrication processes. This allows the manufacturing process to proceed uniformly across the entire substrate without creating pattern density discrepancies, thereby preventing process contamination and polishing failures while maintaining high integration density in the active memory areas.

Inventive Principle:
Principle #26Copying

2Productivity

If the substrate area is fully utilized for memory arrays, then the integration density is maximized, but process contamination occurs due to pattern density discrepancies between different areas

Engineering Contradiction:
Improveintegration densityVSAvoidprocess contamination
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The dummy memory arrays serve multiple functions: they maintain pattern density consistency across the substrate, prevent process contamination, enable uniform polishing processes, and allow full utilization of the substrate area. By making the dummy arrays structurally identical to active memory arrays (same layers, same patterning processes), they fulfill the role of maintaining manufacturing process uniformity while the active areas provide the actual memory functionality, achieving both high productivity and process reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes process contamination and ensures consistent fabrication of memory devices by addressing pattern density discrepancies, enhancing performance and reducing costs.

Implementation Method 1

etching trenches and holes to create conductive structures

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

conformal deposition of metallic and semiconductor layers

Methodology Applied
Scientific EffectConformal deposition:

Data Source

PatentUS20250351354A1Memory devices and methods of manufacturing thereof
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250351354A1 patent drawing
  • US20250351354A1 patent drawing
  • US20250351354A1 patent drawing

AI summary

A method for making memory devices includes forming a first area and a second area of a memory device. In some embodiments, forming at least one of the first area or the second area comprises forming a plurality of first conductive stripes extending along a lateral direction and spaced from one another along a vertical direction. Forming at least one of the first area or the second area further comprises forming a memory layer extending along the vertical direction. Forming at least one of the first area or the second area further comprises forming a semiconductor layer extending along the vertical direction and coupled to a portion of the memory layer. Forming at least one of the first area or the second area further comprises forming second and third conductive stripes extending along the vertical direction.