Pillar-Formed Memory Array Channels for Reliable Vertical NAND

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Solution Overview

Problem

Existing memory array architectures face challenges in efficiently forming vertically-stacked memory cells with reliable electrical connections and structural integrity, particularly in NAND architectures, which affect data retention and access performance.

Innovation Solution

A method involving 'gate-last' processing is employed to form memory arrays with vertically-alternating conductive and insulative tiers, using sacrificial pillars and etching techniques to create channel openings, followed by the formation of conductive lines and memory cells, ensuring robust electrical coupling and structural stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertically-stacked memory cells are formed using conventional methods, then memory array structure is achieved, but electrical connections and structural integrity are unreliable

Engineering Contradiction:

Improveelectrical connections and structural integrityVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Sacrificial pillars are formed in advance at specific locations before creating channel openings. These pillars serve as placeholders that guide subsequent etching processes and ensure precise positioning of channel openings, thereby improving electrical connection reliability and structural integrity before the actual memory cell formation occurs.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Sacrificial pillars act as intermediary structures during the fabrication process. They are temporarily introduced to enable precise formation of channel openings and electrical connections, then removed after serving their guiding function. This intermediary approach allows complex three-dimensional structures to be formed with high precision without directly forming the final structure in a single step.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If gate-last processing is employed, then conductivity and structural integrity are enhanced, but manufacturing process complexity increases

Engineering Contradiction:

Improveconductivity and structural integrityVSAvoidprocessing steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The fabrication process is divided into distinct sequential stages: first forming sacrificial pillars and insulative/conductive tiers, then creating channel openings, and finally forming gates and memory cells. This segmentation allows each stage to be optimized independently, with the gate formation occurring last after all underlying structures are in place, thereby enhancing conductivity and structural integrity while managing complexity through systematic division of the manufacturing process.

Inventive Principle:

Principle #1Segmentation

3Ease of operation

If channel openings are created through etching, then electrical access is improved, but structural stability may be compromised

Engineering Contradiction:

Improveelectrical accessVSAvoidstructural stability

Core Design Contradiction:

Ease of operationVSStrength

Solution Approach 1:

Sacrificial pillars serve as intermediary structures that define the precise locations of channel openings. The etching process removes these sacrificial pillars to create channels for electrical access, while the surrounding insulative and conductive tiers maintain structural stability. The intermediary pillars enable clean, precise channel formation without compromising the overall structural integrity of the vertically-stacked architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the conductivity and structural integrity of memory arrays, improving data retention and access speeds in vertically-stacked memory cells, thereby optimizing performance and reliability.

Implementation Method 1

The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces

Methodology Applied

Scientific EffectDiffusion: Diffusion

Data Source

PatentUS12426265B2Method used in forming a memory array comprising strings of memory cells using pillars

Publication Date: 2025.09.23 MICRON TECHNOLOGY INC

AI summary

A liner is formed laterally-outside of individual channel-material strings in one of first tiers and in one of second tiers. The liners are isotropically etched to form void-spaces in the one second tier above the one first tier. Individual of the void-spaces are laterally-between the individual channel-material strings and the second-tier material in the one second tier. Conductively-doped semiconductive material is formed against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier. The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces.