3D Memory Array Fabrication with Post-Formed Control Logic
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Solution Overview
Problem
Conventional microelectronic device designs face challenges in increasing integration density and performance due to limitations in reducing the size of features and separation distances between them, particularly in memory devices where control logic devices are constrained by processing conditions and spatial arrangements.
Innovation Solution
The method involves forming a microelectronic device structure with a memory array region over a semiconductive base structure containing alignment mark structures, followed by the formation of a control logic region after the memory array region. This allows for independent optimization of control logic device configurations without being limited by the processing conditions required for the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If control logic devices are formed simultaneously with the memory array under conventional processing conditions, then the manufacturing process is simplified, but the control logic device configurations are limited and performance is compromised
Solution Approach 1:
The patent divides the fabrication process into separate stages: first forming the memory array structure, then subsequently forming the control logic devices. This segmentation allows each component to be optimized independently - the memory array can be formed under its required processing conditions, while the control logic devices can be formed later under conditions optimized for their specific requirements, resolving the contradiction between manufacturing simplicity and device performance.
Solution Approach 2:
The patent performs preliminary formation of the memory array structure including substrate preparation, memory cell formation, and interconnect structures before subsequently forming the control logic devices. This preliminary action establishes the foundation first, then allows the control logic to be added in a second stage with optimized processing, thereby achieving both manufacturing feasibility and device performance.
2Adaptability or versatility
If the quantities and dimensions of control logic devices are increased to improve functionality, then more comprehensive control operations are enabled, but the horizontal footprint of the memory device increases
Solution Approach 1:
The patent transitions from planar two-dimensional arrangement of control logic devices to a three-dimensional vertical architecture where control logic devices are stacked above the memory array structure. This dimensional change allows multiple control logic devices to be positioned vertically, providing comprehensive control functionality while maintaining a compact horizontal footprint, thus resolving the contradiction between adaptability and area.
3Productivity
If feature dimensions are reduced to increase integration density, then more features fit in the same area, but processing precision requirements become more stringent and fabrication difficulty increases
Solution Approach 1:
The patent employs advanced parameter changes including forming high-k dielectric materials, using metal gate structures, and implementing strained silicon channels to achieve superior device performance at scaled dimensions. These parameter changes in material properties and structural characteristics enable high integration density while maintaining manufacturability by compensating for the increased precision requirements through enhanced material and device physics.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.