Memory Array Power Domain Partitioning for Standby Energy Reduction

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Solution Overview

Problem

Conventional nonvolatile memory systems consume significant power during standby mode and require substantial power and time to charge up when a memory access is requested, leading to increased power consumption and data access delays in portable and implantable electronic devices.

Innovation Solution

Partitioning the memory into separate power domains and circuits, where only the necessary power domains are powered up during a memory access, reducing the power required to charge up the memory segment and associated circuitry, thereby minimizing power consumption and data access time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the entire nonvolatile memory is powered down during standby mode, then power consumption is reduced, but significant current is required during power-up to charge all capacitances and diodes

Engineering Contradiction:

Improvestandby power consumptionVSAvoidpower-up current

Core Design Contradiction:

Loss of energyVSPower

Solution Approach 1:

The memory array is divided into multiple independently powerable segments or blocks. Each segment can be powered down individually during standby, and only the specific segment containing the requested data address is powered up during memory access. This segmentation allows the system to avoid charging all memory capacitances simultaneously, reducing power-up current requirements while maintaining the ability to access any memory location.

Inventive Principle:

Principle #1Segmentation

2Loss of energy

If the entire nonvolatile memory is powered down during standby mode, then power consumption is reduced, but data access delay time increases due to full memory power-up requirement

Engineering Contradiction:

Improvestandby power consumptionVSAvoiddata access delay

Core Design Contradiction:

Loss of energyVSLoss of time

Solution Approach 1:

The memory is divided into independently controllable segments with separate power domains. During standby, all segments remain powered down except when needed. When a memory access request is received, the system quickly powers up only the specific segment containing the target data, significantly reducing the power-up time compared to charging the entire memory array, thus minimizing data access delay.

Inventive Principle:

Principle #1Segmentation

3Power

If only the necessary memory segment is powered up during memory access, then power consumption and access time are reduced, but the system requires separate power domain control circuitry

Engineering Contradiction:

Improvepower-up powerVSAvoidpower domain control circuitry

Core Design Contradiction:

PowerVSDevice complexity

Solution Approach 1:

A power domain decoder circuit serves as an intermediary between the memory control logic and the segmented memory array. This decoder receives control signals and translates them into appropriate power domain activation signals, enabling selective powering of memory segments. The intermediary simplifies the control architecture by providing a dedicated interface for power management, reducing the overall system complexity despite the added segmentation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8154938B2Memory array power domain partitioning

Publication Date: 2012.04.10 TEXAS INSTRUMENTS INC

AI summary

An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory.