Memory Array Power Signature Suppression via Differential Read
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Solution Overview
Problem
Current memory devices are vulnerable to power signature analysis, a technique that can partially determine stored data by monitoring power consumption patterns, which compromises the security of sensitive information.
Innovation Solution
A semiconductor device with a memory array and output path circuitry that stores data in an even number of cells per bit, using differential access to suppress power signature by resetting output buffers to a consistent logic state during read operations, ensuring consistent power consumption regardless of the data state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory devices are used, then data storage and access functions are provided, but power signature analysis can partially determine stored data, compromising security
Solution Approach 1:
The memory array is divided into multiple cells per bit (even number of cells), where each bit is distributed across multiple cells. This segmentation ensures that no single cell's state can be directly correlated with the logical data state, thereby obscuring power consumption patterns that would otherwise reveal stored data through power signature analysis.
Solution Approach 2:
The patent changes the parameter of power consumption consistency by designing the output path circuitry to maintain consistent power consumption regardless of the actual data state being read. The circuitry resets output buffers to a consistent logic state before reading, ensuring that power consumption remains constant across different data states, thus eliminating detectable power signatures.
2Object-affected harmful factors
If output buffers are reset to consistent logic state during read operations, then power consumption becomes consistent and power signatures are suppressed, but additional control circuitry is required
Solution Approach 1:
The output path circuitry performs a preliminary reset action to a consistent logic state before the actual read operation begins. This preliminary action ensures that any power consumption variations observed during the read operation are due solely to the memory array access rather than variations in output buffer states, thereby suppressing power signatures without requiring complex real-time adjustment circuitry.
Solution Approach 2:
The patent introduces an intermediary reset mechanism in the output path circuitry that acts as a mediator between the memory array read operation and the output buffers. This intermediary component ensures consistent initialization of output buffers before reading, thereby controlling power consumption patterns without requiring direct manipulation of the memory array or complex feedback control systems.
3Object-affected harmful factors
If data is stored in an even number of cells per bit, then power signature suppression is achieved through differential access, but storage density decreases
Solution Approach 1:
The patent applies local quality by using differential access only where necessary for security-critical data storage, while allowing conventional single-cell access elsewhere. Each bit is stored in multiple cells with complementary logic states, creating local differential access patterns that suppress power signatures. This approach balances security enhancement with storage density by applying the multi-cell structure only where power signature suppression is required.
Solution Approach 2:
The memory array combines multiple storage cells per bit in a composite structure where each cell contributes to the differential access mechanism. This composite approach allows the system to achieve both enhanced security through power signature suppression and acceptable storage density by efficiently utilizing the parallel cell structure for both security and storage functions simultaneously.
Data Source
AI summary
A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.