Memory Array Program Progress Indicator for NAND Flash Latency
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Solution Overview
Problem
Managed memory systems face challenges in reducing latency for small read operations in NAND flash devices due to limitations on page buffering, making it impossible to suspend cache program operations after the next memory page is loaded, which affects Quality of Service (QoS) requirements.
Innovation Solution
The implementation of a program progress indicator that tracks the completion of programming levels in multi-level memory cells, allowing for adaptive delay in loading the next page close to the end of the current page's programming, thereby minimizing latency and optimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the next memory page is loaded early into the buffer, then the productivity of the memory system is improved, but the latency for small read operations increases due to premature loading before programming completion
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller monitors the programming status of the current page and uses this information to dynamically control when to load the next page into the buffer. This feedback loop allows the system to optimize the timing of page loading based on actual programming progress, thereby reducing read latency while maintaining high productivity.
Solution Approach 2:
The system transitions from a static page loading approach to a dynamic one where the timing of loading the next page is adjusted based on the programming status of the current page. This dynamic adaptation allows the memory system to optimize performance under varying conditions, resolving the contradiction between productivity and latency.
2Loss of time
If the next memory page is loaded late into the buffer, then the latency for small read operations is reduced, but the productivity of the memory system decreases due to idle buffer time
Solution Approach 1:
The memory controller uses real-time feedback from the programming status to determine the optimal moment to load the next page, ensuring that the buffer is utilized efficiently without premature loading. This feedback mechanism prevents idle buffer time while avoiding the latency issues of early loading.
Solution Approach 2:
The system prepares the next page for loading in advance but executes the actual load operation at the optimal time determined by programming progress. This preliminary preparation combined with timed execution allows the system to minimize both latency and idle time.
3Device complexity
If a fixed delay is used before loading the next page, then the device complexity is reduced, but the adaptability to variations in silicon, temperature, and memory cell aging is lost
Solution Approach 1:
Instead of using a fixed delay, the system implements a feedback-based timing mechanism that monitors programming status and adjusts the loading timing accordingly. This feedback approach provides adaptability to variations in silicon characteristics, temperature, and memory cell aging while maintaining reasonable control complexity.
Solution Approach 2:
The system dynamically changes the timing parameter for page loading based on monitored programming progress and environmental conditions. This parameter adjustment allows the system to adapt to variations in silicon, temperature, and memory cell aging without requiring a completely complex control mechanism.
Data Source
AI summary
A memory device comprises a memory array including multi-level memory cells, buffer circuitry, a memory control unit and a program progress indicator. The memory control unit is operatively coupled to the memory array and configured to load first data into the buffer circuitry and program the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels. The program progress indicator is configured to indicate completion of a programming level as the programming of the multiple programming levels progresses. The memory control unit is further configured to load second data for programming of the multi-level memory cells according to an indication of completion of the program progress indicator.