Memory Array Programming Minimizing Cell Disturbance

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Solution Overview

Problem

In the edge device AI field, flash memory experiences low reliability due to mutual disturbances between memory cells during multi-bit operations, which complicates the storage of multi-level weights and affects the accuracy of in-memory computing (IMC).

Innovation Solution

A memory array programming method that repeatedly generates and compares current errors between memory cells to identify and minimize disturbances by programming the cell with the greatest current error, alternating between cells until they reach their target currents, thereby reducing mutual interference and increasing reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple memory cells are programmed simultaneously, then programming efficiency is improved, but mutual disturbance between memory cells increases

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidprogramming accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-classifying memory cells into groups based on their spatial distribution and disturbance characteristics before programming. Memory cells are organized into multiple groups where cells in the same group have similar disturbance patterns, allowing for optimized programming sequences that address disturbances proactively rather than reactively.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the memory array into multiple independent groups of memory cells. Each group is programmed separately with tailored programming parameters and sequences. This segmentation allows the system to handle multiple cells in parallel while controlling disturbances within each segment, thus maintaining both high productivity and reliability.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If memory cells with high current error are programmed repeatedly, then programming precision is improved, but programming time increases

Engineering Contradiction:
Improvecurrent error precisionVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by focusing programming efforts on memory cells that have not yet reached their target current values. Instead of uniformly programming all cells the same number of times, the system dynamically identifies cells with higher current errors and applies additional programming passes selectively to those specific cells, thereby reducing unnecessary programming operations on already accurate cells.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent implements feedback mechanisms by continuously monitoring the current values of memory cells during programming and comparing them against target values. Based on this feedback, the system dynamically adjusts the programming sequence and determines which cells require additional programming passes. This feedback-driven approach ensures that programming resources are allocated efficiently to cells that need them most.

Inventive Principle:
Principle #23Feedback

3Reliability

If memory cells are programmed in groups with adjacencies, then disturbance management is improved, but device complexity increases

Engineering Contradiction:
Improvedisturbance managementVSAvoidgroup management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating memory cell groups with specific spatial characteristics where adjacent cells are clustered together. Each group has localized programming parameters and sequences tailored to its specific spatial configuration and disturbance profile. This local optimization allows effective disturbance management within each group while maintaining overall system efficiency.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11990187B2Method and apparatus with memory array programming
Publication Date: 2024.05.21 SAMSUNG ELECTRONICS CO LTD
  • US11990187B2 patent drawing
  • US11990187B2 patent drawing
  • US11990187B2 patent drawing

AI summary

Provided is method and apparatus with memory array programming. A memory apparatus may include a memory array including memory cells, and a memory controller, where the memory controller is configured to configured to repeat, for a plurality of times, a generation of a first present time current error between a first present time current and a first target current, both of a first memory cell, a generation of a second present time current error between a second present time current and a second target current, both of a second memory cell, where a greatest among the first present time current error and the second present time current error is a greatest present time current error, and a programming of a select one of the first and second memory cells that has the greatest present time current error.