Memory Array Radiation Immunity via P-Well Minority Charge Dissipation
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Solution Overview
Problem
Conventional methods fail to prevent data corruption in integrated circuits due to single event upsets (SEUs) caused by radiation, as they rely on buried layers with high recombination rates, which actually increase SEU rates by repelling minority carriers.
Innovation Solution
A memory array design featuring p-type transistors in an n-type region with p-wells that form p-n junctions to dissipate minority charge, increasing the perimeter of the n-type region and enhancing the removal of minority carriers generated during SEU strikes, thereby improving radiation immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buried layer with high recombination rate is used to sink minority carriers, then the intention is to reduce SEU impact, but the SEU rate increases due to repulsion of minority carriers
Solution Approach 1:
Instead of using a buried layer to sink minority carriers (conventional approach), the patent inverts the approach by using p-wells to attract and collect minority carriers through p-n junctions. The p-wells are positioned adjacent to the n-type region containing PMOS transistors, creating p-n junctions that actively collect minority carriers rather than repel them, thereby reducing SEU-induced data corruption.
2Reliability
If the perimeter of the n-type region is increased to enhance minority carrier removal, then radiation immunity improves, but the device area increases
Solution Approach 1:
The patent applies local quality by positioning p-wells specifically at critical locations adjacent to the n-type region containing PMOS transistors, rather than uniformly increasing the perimeter throughout. This targeted placement of p-n junctions provides effective minority carrier collection at the most vulnerable areas while minimizing the overall area increase compared to a uniform perimeter expansion approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced p-n junction area effectively attracts and dissipates minority charge, significantly reducing the impact of SEU strikes and improving the performance of CMOS SRAM cells by increasing the area for charge dissipation.
Implementation Method 1
each p-well provides a p-n junction to dissipate minority charge in a portion of the n-type region occupied by a corresponding p-type transistor
Data Source
AI summary
A memory array having improved radiation immunity is described. The memory array comprises a plurality of memory elements, each memory element having an p-type transistor formed in an n-type region; and a plurality of p-wells, each p-well having an n-type transistor coupled to a corresponding p-type transistor to form a memory element of the plurality of memory elements; wherein each p-well provides a p-n junction to dissipate minority charge in a portion of the n-type region occupied by a corresponding p-type transistor and associated with at least two adjacent memory elements. A method of implementing a memory array is also described.