Memory Unit Array Sectioning for Read Speed Equalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face inefficiencies in read speed due to differences in read speeds of data, first reference bits, and second reference bits, leading to decreased overall read speed.
Innovation Solution
A memory device architecture with a unit array comprising multiple sections, each with data and reference regions, where the number of column lines in each section is optimized to minimize capacitance deviation, allowing a sense amplifier to provide read data based on outputs from multiple reference bits, thereby increasing read speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If reference bits are stored in the same memory cell array as data bits, then memory capacity is maximized, but read speed decreases due to different read speeds of data bits and reference bits
Solution Approach 1:
The memory cell array is divided into multiple sections, with each section containing both data memory cells and reference memory cells. This segmentation allows data bits and reference bits to be physically separated into different regions while maintaining equal read speeds by ensuring each section has the same number of column lines.
2Measurement precision
If multiple reference bits are used to determine read data, then data accuracy improves, but read speed decreases due to sequential access requirements
Solution Approach 1:
Multiple reference bits are pre-loaded into different sections of the memory cell array before the read operation begins. During the read operation, all reference bits are simultaneously available in their respective sections, allowing the sense amplifier to compare the read data bit against multiple reference bits in parallel, thus maintaining high read speed while ensuring data accuracy.
3Speed
If the number of column lines in each section is optimized to minimize capacitance deviation, then read speed equalization improves, but device complexity increases
Solution Approach 1:
The number of column lines in each section is carefully calculated and adjusted to minimize capacitance deviation. By optimizing this physical parameter, the patent achieves equal read speeds across all sections without requiring complex control logic or additional circuitry, thus resolving the contradiction between read speed equalization and device complexity.
Data Source
AI summary
A memory device includes a memory array including a plurality of sections, each including a plurality of memory cells and at least one reference cell. The memory device may also include a plurality of sense amplifier circuits respectively corresponding to the plurality of sections, and a plurality of switch circuits, each switch circuit connected between a respective section and sense amplifier circuit. Each switch circuit may be configured to select between communicatively connecting a first column of memory cells or a reference cell to a corresponding sense amplifier.