Memory Array Power Retention During Reset for Data Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Volatile memory, such as DRAM, loses stored data during a power outage or reset, failing to meet the need for quick boot applications where data retention is required.
Innovation Solution
A memory storage apparatus with a controller circuit that receives reset and trigger signals, performing a reset operation while maintaining power to the memory array during a reset period, ensuring data accuracy post-reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a reset operation is performed on volatile memory, then the memory is cleared and prepared for new operations, but the stored data is lost
Solution Approach 1:
The patent applies preliminary action by performing a self-refresh operation before the reset operation on a first portion of the memory array. This preliminary refresh maintains the data in the selected row during the subsequent reset operation, allowing the reset to clear other portions of memory while preserving specific data that needs to be retained for quick boot operations.
2Loss of time
If power is cut to the memory array during reset, then the reset operation completes faster, but data accuracy is compromised
Solution Approach 1:
The patent segments the memory array into multiple portions and applies different operations to different segments. The first portion undergoes self-refresh to maintain data, while the second portion undergoes reset. This segmentation allows the system to maintain data accuracy for critical portions while still achieving reset functionality for other portions, effectively resolving the contradiction between reset speed and data accuracy.
Solution Approach 2:
The patent applies local quality by providing different power supply conditions to different portions of the memory array during the reset period. The first portion receives continued power supply to maintain data accuracy, while the second portion has power cut to enable proper reset. This localized differential treatment resolves the contradiction by maintaining data accuracy where needed while enabling fast reset where appropriate.
Data Source
AI summary
A memory storage apparatus, including a memory array and a controller circuit, is provided. The memory array is configured to store data. The controller circuit is coupled to the memory array. The controller circuit configured to receive a reset signal and a trigger signal. The controller circuit performs a reset operation according to the reset signal. The controller circuit maintains a power supply to the memory array according to the trigger signal during a reset period.