Memory Array Resistance Mapping for Stable MAC Voltage Levels
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Solution Overview
Problem
In-memory computing systems face issues with pattern variation in voltage levels due to varying resistance patterns of memory cells, leading to inconsistent data values during MAC operations.
Innovation Solution
The resistance of memory cells is standardized to be one-Nth of a reference resistance based on their data values, ensuring consistent voltage levels for different data combinations, thereby reducing pattern variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells have varying resistance patterns based on data values, then multi-level data storage is achieved, but voltage level consistency deteriorates during MAC operations
Solution Approach 1:
The patent applies parameter changes by adjusting the resistance values of memory cells to follow a standardized geometric progression pattern where each resistance is one-Nth of a reference resistance. This parameter standardization ensures that despite storing multi-level data, the voltage levels during MAC operations remain consistent and predictable, resolving the contradiction between data storage capacity and voltage consistency.
2Adaptability or versatility
If resistance values vary across different data values, then multi-level coding is enabled, but pattern variation in voltage levels increases
Solution Approach 1:
The patent implements parameter changes by establishing a standardized resistance value system where each data value corresponds to a specific resistance that is one-Nth of a reference resistance. This standardized parameter mapping enables multi-level coding while maintaining stable voltage levels during computations, as the geometric progression ensures consistent voltage division ratios regardless of the specific data pattern.
3Reliability
If memory cells use standardized resistance values (one-Nth of reference resistance), then voltage level consistency is improved, but resistance variation for data encoding is reduced
Solution Approach 1:
The patent resolves this contradiction by using a geometric progression series where resistance values are standardized to one-Nth of a reference resistance. This creates discrete, well-defined resistance levels that provide both consistency for reliable voltage output and sufficient differentiation for encoding multiple data values. The standardized parameters enable predictable voltage division while maintaining the ability to represent different data states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes voltage levels across varying data patterns, enhancing the reliability and accuracy of in-memory computing operations.
Implementation Method 1
Each of the memory cells has multi-levels of data values. A resistance of each of the memory cells is associated with a data value of the data stored in the corresponding memory cell.
Implementation Method 2
the resistance of memory cells is standardized to be one-Nth of a reference resistance based on their data values, ensuring consistent voltage levels for different data combinations
Data Source
AI summary
A memory device includes a current source and a memory array. The current source is configured to provide a current to a first node. The memory array is coupled to the current source at the first node. The memory array includes memory cells. First terminals of the memory cells are coupled to the first node. Each of the memory cells has a first resistance in response to having a first data value, and has a second resistance in response to having a second data value. The second data value is N times the first data value. The second resistance is approximately one-Nth of the first resistance, for N being a positive integer larger than one. A method of operating a memory device is also disclosed herein.