Memory Array Partitioning for Secure In-Memory Bit-Vector Access
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Solution Overview
Problem
Existing memory systems face challenges in securing data transfer by encrypting/decrypting data, which affects system performance and adds circuit complexity, and external processing resources often require significant power consumption and do not conform to memory array pitch rules.
Innovation Solution
A processor-in-memory (PIM) device with a memory array that includes a first portion inaccessible to external devices and a second accessible portion, where bit-vector operations are performed internally without transferring data across a bus, using sensing circuitry formed on the same pitch as memory cells to reduce power consumption and protect data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data encryption/decryption is used to secure data transfer, then data security is improved, but system performance deteriorates and circuit complexity increases
Solution Approach 1:
The patent extracts the data processing function from external processing resources and relocates it to the memory array itself. By implementing processing circuitry within the memory device, data operations are performed internally without requiring external processors, thereby reducing overall system complexity while maintaining security through internal access controls
Solution Approach 2:
The memory array is designed to serve multiple functions: data storage, data processing, and security control. The processing circuitry integrated within the memory array enables it to perform computational tasks while maintaining secure access through row register controls, eliminating the need for separate dedicated processing units
2Reliability
If data encryption/decryption is used to secure data transfer, then data security is improved, but system performance deteriorates
Solution Approach 1:
The patent removes the data transfer step entirely by performing processing operations directly within the memory array. This eliminates the need for data to traverse external buses and be subjected to encryption/decryption operations, thereby maintaining security while significantly improving processing speed and system performance
Solution Approach 2:
The row register acts as an intermediary control mechanism that manages access to specific rows of memory cells. It enables secure data access by controlling which rows are accessible to external devices and which remain internal, providing security without requiring time-consuming encryption operations
3Productivity
If external processing resources are used, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent merges the storage function and processing function into a single integrated memory array. By combining memory cells with processing circuitry in the same physical structure, data processing occurs locally without requiring data to be transferred to external processing resources, thereby reducing power consumption while maintaining processing capability
Solution Approach 2:
The memory array performs self-processing by executing operations directly on stored data through integrated processing circuitry. This self-service capability eliminates the need for external processing resources, significantly reducing power consumption while maintaining full processing functionality
4Productivity
If bit-vector operations are performed internally in memory array, then parallelism is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory array into accessible and inaccessible portions, with specific rows designated for external access and other rows reserved for internal processing. This segmentation enables parallel operations where data can be processed in different regions simultaneously, improving parallelism while managing complexity through structured organization
Solution Approach 2:
The patent introduces a new dimension of organization by creating inaccessible rows that are not accessible to external devices but are accessible to internal processing circuitry. This dimensional separation enables internal parallel processing operations without affecting external data access, improving productivity while containing complexity within designated internal structures
Data Source
AI summary
Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.