Memory Array Partitioning for Secure In-Memory Logic Access
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Solution Overview
Problem
Existing memory systems face challenges in securing data transfer by encrypting/decrypting, which affects system performance and adds circuit complexity, and external processing resources often fail to conform to memory array pitch rules, leading to increased power consumption and chip size.
Innovation Solution
A processor-in-memory (PIM) device with a memory array that includes a first portion inaccessible to external devices and a second accessible portion, utilizing sensing circuitry to perform logical operations internally without data transfer across buses, thus protecting data and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is encrypted/decrypted to secure data transfer, then data security is improved, but system performance deteriorates and circuit complexity increases
Solution Approach 1:
The patent extracts the processing function from external processors and moves it directly into the memory array. By performing logical operations within the memory cells themselves, the system eliminates the need to transfer data out for processing, thereby maintaining security without the performance penalty of encryption/decryption cycles.
Solution Approach 2:
The patent merges the storage function and processing function into a single integrated structure. The memory array simultaneously stores data and performs logical operations on that data, eliminating the separate encryption/decryption hardware and associated performance overhead.
2Productivity
If external processing resources are used, then processing capability is improved, but power consumption increases and chip size increases
Solution Approach 1:
The patent combines storage and processing functions into the memory array itself. By performing logical operations within the memory cells using their existing structure, the system eliminates the need for separate external processing resources, thereby reducing power consumption and chip size while maintaining processing capability.
Solution Approach 2:
The patent makes the memory array multi-functional by enabling it to both store data and perform logical operations. This universal functionality eliminates the need for dedicated processing resources, reducing overall system power consumption and footprint.
3Adaptability or versatility
If data is transferred across buses for processing, then processing flexibility is improved, but data security deteriorates due to detectability
Solution Approach 1:
The patent merges storage and processing within the memory array, eliminating data transfer across buses. By performing logical operations in-place within the memory cells, the system maintains processing flexibility while preventing data from being exposed on external buses where it could be detected or intercepted.
4Device complexity
If processing resources are external to memory array, then functional separation is improved, but chip size increases
Solution Approach 1:
The patent merges the storage function and processing function into the same physical location (the memory array). This integration eliminates the need for separate external processing resources, thereby reducing chip size while maintaining the necessary functional capabilities through in-array logical operations.
Data Source
AI summary
Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.