Non-volatile Memory Array Segmentation for Charge Pump Reduction
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Solution Overview
Problem
Conventional non-volatile memory cell arrays require large charge pumps to supply high voltages across entire rows of memory cells, leading to significant space consumption and power usage.
Innovation Solution
The memory device is segmented into multiple planes of non-volatile memory cells, with gate lines extending only across rows within each plane, allowing data to be divided into fractional-words and programmed across separate planes, reducing the need for large charge pumps by only requiring high voltage supply across half a row during programming and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate lines extend across entire rows of memory cells in a conventional array, then the memory array can be fully addressed, but the charge pump size and power consumption increase significantly
Solution Approach 1:
The memory array is divided into multiple planes, with each plane containing a subset of memory cells. Gate lines (word lines, control gate lines, erase gate lines) extend only across rows within each plane rather than across the entire array. This segmentation allows the charge pump to supply high voltages to smaller subsets of cells simultaneously, reducing the required charge pump size and power consumption while maintaining full array addressability through the controller's ability to select and operate on individual planes.
2Productivity
If the charge pump supplies high voltage across the entire row, then all memory cells in the row can be programmed simultaneously, but power consumption increases
Solution Approach 1:
The array is segmented into multiple planes where each plane can be independently programmed. The controller divides words of data into fractional-words and programs each fractional-word into a different plane. This allows the charge pump to operate at full power on smaller subsets of cells in parallel across multiple planes, achieving similar overall throughput while reducing the power burden on any single charge pump instance.
Solution Approach 2:
Instead of programming the entire row in a single operation across the full array, the system performs partial programming operations on fractions of words across multiple planes. Each plane undergoes a complete programming cycle with full voltage application, but since planes are processed sequentially or in smaller parallel groups, the instantaneous power consumption is reduced compared to applying voltage across the entire array simultaneously.
3Device complexity
If gate lines extend across the entire array, then address decoding is simplified, but the charge pump must be larger to supply voltage across the full distance
Solution Approach 1:
The memory array is divided into multiple planes with gate lines extending only across rows within each plane. The controller manages address decoding by selecting specific planes and applying appropriate address offsets. This segmentation reduces the physical distance over which gate lines must extend, thereby reducing the power required by the charge pump to supply high voltages, while the controller's plane selection logic maintains efficient address decoding.
4Area of stationary object
If the memory array is divided into multiple planes with separate gate lines, then charge pump size is reduced, but programming time for a complete word increases due to multiple operations
Solution Approach 1:
The memory array is divided into multiple planes that can be independently programmed. The controller divides words of data into fractional-words and programs each fractional-word into a different plane. While each individual plane requires a complete programming cycle, the ability to pipeline operations across multiple planes and the reduced charge pump size enabling faster voltage establishment partially offset the increased total programming time, making the trade-off acceptable for the significant reduction in charge pump area and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes the size and power consumption of the charge pump, while maintaining similar programming time and performance, although it may extend programming time for an entire word of data due to the need for two operations, which can be mitigated by the <=N'0'bit-programming method.
Implementation Method 1
The cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 28 with the other terminals equal to zero volts. Electrons tunnels from the floating gate 24 into the erase gate 28
Implementation Method 2
The cell 10 is programmed, through source side hot electron programming mechanism, by applying a high voltage on the coupling gate 26, a high voltage on the source line 14, a medium voltage on the erase gate 28, and a programming current on the bit line 20. A portion of electrons flowing across the gap between the word line 22 and the floating gate 24 acquire enough energy to inject into the floating gate 24
Data Source
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AI summary
A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.