3D Memory Cell Array Segmentation for Capacity and Cell Current
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Solution Overview
Problem
Existing memory devices with three-dimensionally disposed memory cells face limitations in increasing the number of memory holes and electrode layers due to restricted chip size, which hampers the enhancement of storage capacity.
Innovation Solution
The memory device employs a stacked structure of multiple memory cell arrays, each with its own electrode layers and semiconductor pillars, interconnected via contact plugs and connection pads, allowing for increased storage capacity without the need for continuous stacking of 192 electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of electrode layers and memory holes is increased to enlarge storage capacity, then storage capacity is improved, but device complexity and manufacturing difficulty increase due to restricted chip size
Solution Approach 1:
The memory device is divided into multiple independent memory cell arrays (first memory cell array, second memory cell array, etc.), each with its own electrode layers and semiconductor pillars. This segmentation allows the total storage capacity to be distributed across multiple smaller arrays, reducing the complexity of manufacturing any single array while achieving the same total capacity as a single large array with many electrode layers.
Solution Approach 2:
Instead of increasing storage capacity by stacking more electrode layers in the vertical dimension (which increases device complexity), the patent transitions to a horizontal arrangement of multiple memory cell arrays. This dimensional shift allows capacity expansion without proportionally increasing the complexity of individual array structures.
2Quantity of substance
If the number of electrode layers is increased to achieve higher storage capacity, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
By segmenting the memory device into multiple memory cell arrays with fewer electrode layers each, the manufacturing precision required for any single array is reduced. Each array can be manufactured with standard precision levels, avoiding the need for extremely high precision that would be required to manufacture a single array with 192 electrode layers.
3Quantity of substance
If the number of electrode layers is increased to enlarge storage capacity, then storage capacity is improved, but the risk of cell current reduction due to semiconductor pillar resistance increases
Solution Approach 1:
Segmenting the memory device into multiple arrays reduces the number of electrode layers per array, which in turn reduces the length of semiconductor pillars in each array. Shorter pillars have lower resistance, thereby maintaining higher cell current and improving reliability while still achieving the desired total storage capacity through the combined arrays.
Data Source
AI summary
A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.