Nonvolatile Memory Array Segmentation for Independent Cell Reading
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Solution Overview
Problem
Conventional nonvolatile memory (NVM) arrays face challenges in efficiently reading and programming memory cells, particularly in NAND architecture where all cells in a column must conduct to allow current flow, making it difficult to determine the state of a specific memory cell without affecting unselected rows.
Innovation Solution
The implementation of a nonvolatile memory array structure where each memory cell has a first and second gate structure overlying body regions, with drain regions electrically connected to a bitline segment, and source regions formed to isolate body regions, allowing for independent control and reading of memory cells within the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells in NAND architecture are connected in series within columns, then current can flow through the column only when all cells conduct, but it becomes difficult to determine the state of a specific memory cell without affecting unselected rows
Solution Approach 1:
The patent divides the memory array into distinct blocks with isolated body regions, where each block can be independently controlled. This segmentation allows selective reading of specific memory cells without affecting other rows, resolving the detection difficulty while maintaining the series connection reliability for data storage.
Solution Approach 2:
The patent applies different conductivity types to different regions (n-type for bitlines, p-type for body regions) and creates locally isolated body regions with specific doping characteristics. This local quality differentiation enables precise control and detection of individual memory cells within the NAND architecture while maintaining overall system reliability.
2Ease of operation
If wordline potentials of unselected rows are adjusted to limit current flow, then current can be controlled through unselected rows, but the complexity of controlling and measuring memory cell states increases
Solution Approach 1:
By segmenting the memory array into isolated blocks with physically separated body regions, the patent eliminates the need for complex potential adjustments across entire rows. Each block can be independently controlled with simpler voltage schemes, reducing operational complexity while maintaining ease of current control within selected cells.
Solution Approach 2:
The patent extracts the body regions of unselected rows from the conduction path by creating physically isolated regions with opposite conductivity types. This removal of active body regions from the measurement path simplifies control mechanisms, as current can only flow through blocks where body regions are not isolated, automatically preventing interference with unselected rows.
3Reliability
If all memory cells in a column must conduct for current flow in NAND architecture, then data storage reliability is improved, but the ability to independently read specific cells is reduced
Solution Approach 1:
The patent segments the memory array into independently controllable blocks with isolated body regions. This allows the series connection requirement for data storage reliability to be maintained within each block, while the segmentation enables independent reading of specific blocks without requiring all cells in the entire column to be active, thus improving ease of operation.
Solution Approach 2:
By creating local regions with specific conductivity types and isolation characteristics, the patent enables independent control of individual memory blocks. The local quality differences (n-type vs p-type regions, isolated vs connected body regions) allow selective activation of specific cells or blocks while maintaining the series connection reliability within active blocks.
Data Source
AI summary
An electronic device includes a first memory cell and a second memory cell, of a nonvolatile memory array. The first memory cell includes a body region, a gate structure, a source region, and a drain region. The second memory cell includes a body region, a gate structure, a source region, and a drain region. In one embodiment, the body of the second memory cell is physically isolated from the body region of the first memory cell. A bitline segment is electrically connected to the drain region of the first memory cell and to the drain region of the second memory cell.