Selective Data Writing in Memory Arrays via Column Segmentation
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Solution Overview
Problem
Existing data writing methods in semiconductor memory require additional circuit structures or operations to prevent changes in non-target memory cells, leading to increased complexity and inefficiency when only a part of the data needs to be written, as they typically involve writing or reading 128 bits synchronously.
Innovation Solution
A data writing method that reads old data from a target column, updates it based on target data bit information to generate new data, and writes the new data back into the target column, allowing for selective data modification without additional hardware structures by using existing memory arrays and control logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional synchronous writing method is used to write data into memory array, then data transmission rate is improved, but device complexity increases when only partial data needs to be written due to additional circuit structures required to protect non-target memory cells
Solution Approach 1:
The patent divides the 128-bit data column into multiple segments, allowing selective writing to only the required portion (e.g., 8-bit target column) while leaving other segments unchanged. This segmentation enables partial data writing without requiring additional protection circuits for the entire 128-bit column, thus reducing device complexity while maintaining high data transmission rate.
2Manufacturing precision
If additional circuit structures are added to protect non-target memory cells during partial data writing, then data accuracy is improved, but device complexity increases
Solution Approach 1:
Instead of protecting all 128-bit memory cells during writing operations, the patent applies writing operations only to the necessary partial portion (e.g., 8-bit target column). This partial action approach ensures data accuracy for the target cells without requiring additional protection circuits for the entire column, thereby avoiding increased device complexity.
3Speed
If synchronous reading and writing of 128-bit data is performed, then data transmission speed is improved, but efficiency decreases when only a small portion of data needs to be written
Solution Approach 1:
The patent segments the 128-bit data column into a target column (e.g., 8-bit) and non-target columns, enabling selective writing operations. This allows the system to maintain the high-speed synchronous writing capability while writing only the necessary 8-bit portion, thereby improving writing efficiency without sacrificing data transmission speed.
Data Source
AI summary
A data writing method and a memory, in which the data writing method is used for writing data to a memory array of the memory. The data writing method includes that: old data is read from a target column of the memory array; the old data is updated according to data to be written which carries target data bits information to generate new data; and the new data is written into the target column, in which the memory includes a plurality of data columns, the data is required to be written into the target column, and the target column includes a part of the data columns.