Memory Array Segmentation for SLC Endurance and MLC Reliability
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in achieving high endurance for single-level cell (SLC) blocks while maintaining high reliability for multi-level cell (MLC) blocks, as the process of optimizing for one type often compromises the other, leading to issues like program disturb and varying endurance and reliability across different memory states.
Innovation Solution
The solution involves forming distinct regions for SLC and MLC blocks within a memory array, using different ion concentrations and shallow trench isolation structures to optimize each type, and adjusting read parameters based on usage, such as varying the bit line voltage during read operations to account for increased resistance due to trapped charge over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the memory array uses a uniform structure for all blocks, then manufacturing is simpler, but endurance and reliability vary across different memory states
Solution Approach 1:
The memory array is divided into distinct first and second blocks with different structures. The first block is configured for high endurance operation while the second block is configured for high reliability operation. This segmentation allows each block to be optimized independently for its specific function, resolving the contradiction between manufacturing simplicity and reliability consistency.
Solution Approach 2:
Different blocks within the memory array are given different local structures and characteristics. The first block has parameters optimized for endurance (such as doping concentrations and threshold voltage ranges) while the second block has parameters optimized for reliability. This local differentiation allows each region to perform its specific function optimally.
2Reliability
If MLC blocks are optimized for high reliability, then data retention is improved, but program disturb increases due to closely packed states
Solution Approach 1:
The memory array separates MLC blocks into two distinct groups: first MLC blocks optimized for reliability with closely packed threshold voltage states, and second MLC blocks optimized for endurance with different structural parameters. This segmentation isolates the program disturb issue to specific blocks while preserving high reliability in others.
Solution Approach 2:
Each MLC block type has locally optimized characteristics. The first MLC blocks have threshold voltage distributions and structural parameters tailored for maximum reliability, while the second MLC blocks have different parameters that reduce program disturb effects. This local optimization allows both conflicting requirements to be satisfied in different regions.
3Duration of action of moving object
If SLC blocks are optimized for high endurance, then program/erase cycles increase, but reliability decreases compared to MLC blocks
Solution Approach 1:
The memory array is segmented into SLC blocks optimized for endurance and MLC blocks optimized for reliability. This segmentation allows the system to provide both high-endurance storage and high-reliability storage in the same device, with each block type serving its specific purpose without compromising the other.
Solution Approach 2:
SLC blocks are given local structural optimizations including specific doping concentrations and threshold voltage ranges that maximize endurance. These local characteristics differ from MLC blocks, allowing SLC blocks to achieve superior program/erase cycle life while MLC blocks maintain better data retention for long-term storage.
4Ease of operation
If a single read voltage is used for all blocks, then operation is simpler, but accurate threshold voltage measurement deteriorates over time due to trapped charge
Solution Approach 1:
The read operation dynamically adapts the bit line voltage based on the specific block being read and the number of program/erase cycles it has undergone. First blocks use different read voltages than second blocks, and voltages are adjusted over time to compensate for trapped charge effects. This dynamic adjustment maintains measurement precision while preserving operational simplicity through automated voltage selection.
Solution Approach 2:
The read voltage parameter is changed based on block type and usage history. First blocks may use higher read voltages to compensate for different charge trapping characteristics, while second blocks use lower voltages. The system automatically selects appropriate voltage parameters to maintain accurate threshold voltage measurement despite variations in block age and usage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the endurance of SLC blocks and reliability of MLC blocks by tailoring processing steps and parameters for each type, reducing program disturb and maintaining accurate threshold voltage measurement over the lifespan of the memory cells.
Implementation Method 1
Ions having a first concentration are implanted in the substrate for source/drain regions in the first region. Ions having a second concentration are implanted in the substrate near the source/drain regions in the first region. The conductivity type of the first concentration is opposite the conductivity type of the second concentration.
Data Source
AI summary
Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.