Memory Array Segmentation for Plate Voltage Regulation
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Solution Overview
Problem
Current memory devices face high current draw during sequential access and writing operations to large sections of memory arrays, particularly in modes like Fast Zero, which can be inefficient and resource-intensive.
Innovation Solution
Implementing the Fast Zero mode, which uses counters to generate internal memory addresses for sequential access, allowing for writing logical zeros to multiple memory cells without using the input/output interface, and alternating between sections of opposite polarity to reduce current demand.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If sequential access to each memory cell is implemented for testing or large section access, then memory array accessibility is improved, but current draw increases significantly
Solution Approach 1:
The memory array is divided into multiple sections, each with its own set of bit lines. During sequential access operations, only the bit lines for the current section being accessed are activated, while other bit lines remain inactive. This segmentation allows the system to maintain full memory array accessibility while significantly reducing current draw by limiting the number of simultaneously active bit lines to just one section worth, rather than the entire array.
2Productivity
If Fast Zero mode is used to write logical zeros to multiple memory cells quickly, then writing speed is improved, but current demand increases
Solution Approach 1:
The memory array is divided into multiple sections for Fast Zero operations. The system writes logical zeros to one section at a time using dedicated bit lines for each section. By segmenting the write operation across multiple sections rather than activating all bit lines simultaneously, the system achieves high-speed bulk writing while limiting current demand to levels comparable to normal single-cell access operations.
Solution Approach 2:
Fast Zero mode implements periodic action by systematically cycling through sections of the memory array in a predetermined sequence. Each section receives a write pulse at regular intervals, allowing the system to maintain high productivity through continuous operation while managing current demand through the periodic, rather than simultaneous, activation of bit lines across different sections.
3Productivity
If all bit lines are activated simultaneously for bulk memory access, then access efficiency is improved, but voltage regulation becomes difficult
Solution Approach 1:
The memory array is divided into multiple sections, each with dedicated bit lines. During bulk access operations, sections are activated sequentially rather than simultaneously. This segmentation approach maintains high access efficiency by keeping bit lines ready and responsive while dramatically simplifying voltage regulation requirements, as the plate voltage regulator only needs to handle the load of a single section at a time rather than the entire array.
Data Source
AI summary
A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.