Memory Array Error Correction via Segmented Scrubbing
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Solution Overview
Problem
Current memory devices face challenges in correcting errors, particularly with on-die data protection components being unable to handle multi-bit errors and introducing additional errors during correction attempts, while system-level scrubbing operations are infrequent, leading to accumulation of errors that can render correctable errors uncorrectable, especially in critical applications like server clusters and hyperscalers.
Innovation Solution
Implementing a system where registers at memory devices indicate corrupted codewords to a system-level component, allowing for opportunistic patrol scrubbing operations and directing on-die scrubbing operations at identified error-prone areas, thereby reducing the accumulation of errors and enhancing error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die data protection components are used to correct errors, then single-bit errors can be corrected, but multi-bit errors cannot be handled and additional errors may be introduced during correction attempts
Solution Approach 1:
The patent divides error correction into two levels: on-die correction for single-bit errors and system-level patrol scrubbing for multi-bit errors. This segmentation allows each level to handle appropriate error types, preventing on-die components from attempting to correct multi-bit errors which could introduce additional errors.
Solution Approach 2:
The patent introduces patrol scrubbing operations as an intermediary mechanism between memory writes and reads. These operations detect and correct multi-bit errors before they can cause data corruption, while the on-die components continue to handle single-bit errors, thus preventing additional errors from being introduced.
2Reliability
If system-level scrubbing operations are performed infrequently, then system resource usage is reduced, but errors accumulate and become uncorrectable
Solution Approach 1:
The patent implements patrol scrubbing operations that periodically scan and correct errors before they can accumulate to uncorrectable levels. By performing these operations in advance, the system prevents error accumulation without requiring continuous monitoring, thus balancing reliability with resource usage.
Solution Approach 2:
The patent employs periodic patrol scrubbing operations at system-level intervals rather than continuous monitoring. This periodic approach maintains error correction effectiveness by catching errors before they become uncorrectable, while minimizing system resource usage by not requiring constant operation.
3Reliability
If on-die scrubbing operations are performed frequently, then error accumulation is reduced, but system resource consumption and downtime increase
Solution Approach 1:
The patent segments scrubbing operations into on-die and system-level components with different frequencies and scopes. On-die scrubbing handles local errors quickly with minimal impact, while system-level patrol scrubbing performs comprehensive checks less frequently, thus preventing error accumulation without causing excessive downtime.
Solution Approach 2:
The patent implements partial scrubbing at the on-die level that targets specific error-prone areas rather than performing exhaustive full-array scrubbing frequently. This partial action approach reduces error accumulation in critical regions while minimizing the impact on system availability and resource consumption.
Data Source
AI summary
Methods, systems, and devices for memory operations are described. A codeword may be associated with a set of data and stored in a memory device may be detected as having a plurality of bit errors. Based on detecting the plurality of bit errors in the codeword, an address of the codeword may be stored and an indication that at least one codeword stored in the memory device has a plurality of bit errors may be indicated. Based on indicating that at least one codeword in the memory device has a plurality of bit errors, a write command for writing, to the memory device, a second codeword associated with the set of data may be received. Additionally, or alternatively, a command that triggers an error correction operation at an address range of the memory device may be received at a memory device.