Memory Array Data Reversal via Shared I/O Lines
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Solution Overview
Problem
Existing methods for reversing data in memory arrays are inefficient, often requiring data to be moved externally for processing, which is cumbersome and consumes significant power and bandwidth, especially when dealing with large data sets.
Innovation Solution
The implementation of an apparatus with shared input/output lines and sensing components that allow for the selective coupling of data within the memory array, enabling the reversal of data patterns without external processing resources, thereby reducing power consumption and improving parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is moved externally for processing, then data reversal can be performed, but power consumption and bandwidth usage increase significantly
Solution Approach 1:
The memory array performs data reversal operations using its own internal sensing components and bit lines without requiring external processing resources. The sensing components are configured to selectively couple and reverse data patterns within the array, making the system self-sufficient for this operation and eliminating the need to move data externally for processing.
Solution Approach 2:
The sensing components in the memory array are designed to perform multiple functions: normal data sensing/readout and data reversal operations. By configuring these existing components to perform both functions, the patent eliminates the need for separate external processing resources, thereby reducing power consumption and bandwidth usage while maintaining data reversal capability.
2Ease of operation
If data is moved externally for processing, then data reversal can be achieved, but processing time increases
Solution Approach 1:
The memory array performs data reversal operations using its own internal sensing components and bit lines without requiring external processing resources. This self-service approach eliminates data movement overhead and external processing delays, significantly reducing the time required to reverse data patterns.
Solution Approach 2:
The sensing components are pre-configured and positioned within the memory array to enable direct manipulation of data patterns. This preliminary arrangement of sensing components allows immediate data reversal operations without the need to first move data to external processors, thereby reducing processing time.
3Ease of operation
If external processing resources are used, then data reversal can be performed, but device complexity increases
Solution Approach 1:
The memory array performs data reversal operations using its own internal sensing components and bit lines without requiring external processing resources. This self-service approach simplifies the overall system architecture by eliminating the need for external processing units, data movement interfaces, and associated control logic.
Solution Approach 2:
The sensing components in the memory array are designed to perform multiple functions: normal data sensing/readout and data reversal operations. By configuring these existing components to perform both functions, the patent reduces system complexity compared to using dedicated external processing resources for each operation.
Data Source
AI summary
Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.