Memory Cell Array Layout With Shield Lines for Low Parasitic Capacitance
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Solution Overview
Problem
The close spacing of conductors in memory cell arrays leads to undesired parasitic capacitance, which adversely impacts the design and operation of memory circuitry, a challenge in fabricating ever-smaller and closer-spaced components.
Innovation Solution
The implementation of arrays of memory cells comprising a capacitor and a transistor, with alternating columns of digitlines and conductive shield lines to reduce parasitic capacitance, and the use of self-aligned double patterning techniques to form these components, such as spacer double patterning, to achieve closer conductor spacing without increasing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conductors are placed closer together to reduce memory cell size, then memory cell density is improved, but parasitic capacitance increases
Solution Approach 1:
Conductive shield lines are introduced as intermediary elements positioned between adjacent digitlines. These shield lines act as mediators that block parasitic capacitance coupling between neighboring digitlines while allowing the digitlines to maintain close spacing for high density memory cell design.
Solution Approach 2:
The conductive interconnect structure is segmented into alternating columns of digitlines and conductive shield lines. This segmentation allows the shield lines to be positioned strategically between digitlines to reduce parasitic capacitance without requiring large spacing between functional conductors.
2Manufacturing precision
If self-aligned double patterning is used to form conductors, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The method uses preliminary patterning actions where spacer material is deposited and etched to define conductor positions before final conductor formation. This preliminary action establishes precise alignment references that guide subsequent fabrication steps, achieving sub-30nm precision through multiple simpler sequential operations rather than requiring single-step high-precision patterning.
Solution Approach 2:
The self-aligned double patterning process uses the previously formed structures (such as spacer lines) to automatically define the positions of subsequent conductors without requiring additional alignment steps. The process serves itself by using formed features as templates for the next features, eliminating the need for complex external alignment equipment and procedures.
Data Source
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AI summary
An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive shield lines. In a second level above the first level there are rows of transistor wordlines. In a third level above the second level there are rows and columns of capacitors. In a fourth level above the third level there are rows of transistor wordlines. In a fifth level above the fourth level there are alternating columns of digitlines and conductive shield lines. Other embodiments and aspects are disclosed, including method.