Memory Array Data Converters for Sparse Neural Network Activations
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Solution Overview
Problem
Conventional digital-to-analog (DAC) and analog-to-digital (ADC) converters in cross-bar memory arrays for neural networks are costly in terms of area and power, offsetting the benefits of analog-domain operations due to their significant resource requirements.
Innovation Solution
The implementation of optimized DAC and ADC systems that utilize digital and analog comparators to determine threshold-exceeding data, allowing for efficient transmission and conversion of sparse neural network activation data, reducing the need for unnecessary circuit operations and power consumption by clamping small non-zero values to zero, thereby optimizing data conversion in memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DAC and ADC converters are implemented in cross-bar memory arrays, then data conversion functionality is achieved, but circuit area and power consumption increase significantly
Solution Approach 1:
The patent segments the data conversion process by implementing separate DAC units for each word line and separate ADC units for each bit line in the cross-bar memory array. This segmentation allows independent operation of conversion units, enabling area optimization by only activating necessary converters during specific operations rather than maintaining all converters continuously active.
Solution Approach 2:
The patent employs dynamic control of DAC and ADC units through enable signals that activate only the necessary conversion units based on the current operational requirements. This dynamic activation reduces the effective circuit area in use at any given time while maintaining full conversion functionality when needed, directly addressing the area-power tradeoff.
2Reliability
If conventional DAC and ADC converters are implemented in cross-bar memory arrays, then data conversion functionality is achieved, but power consumption increases significantly
Solution Approach 1:
By segmenting the conversion functionality into distributed DAC units per word line and ADC units per bit line, the patent enables selective activation of only the necessary conversion units for each operation. This segmentation reduces overall power consumption by avoiding simultaneous operation of all converters, while maintaining reliable data conversion functionality when required.
Solution Approach 2:
The dynamic enable/disable control of DAC and ADC units based on operational needs allows the system to minimize power consumption during idle or partial-operation states while ensuring full conversion functionality is available when required. This dynamic power management directly resolves the contradiction between maintaining functionality and reducing power usage.
3Reliability
If all DAC and ADC units are activated for data conversion, then complete data processing is achieved, but conversion cycle time increases
Solution Approach 1:
The segmented architecture with independent DAC units per word line and ADC units per bit line enables parallel processing of multiple data streams simultaneously. This segmentation allows the system to activate only the specific conversion units needed for the current operation, completing data processing faster by avoiding the sequential activation of all units while still achieving complete processing for the active data paths.
Data Source
AI summary
In a particular implementation, a method of data conversion is disclosed. For example, for each word-line of a plurality of word-lines in a memory array, the method includes: 1) determining, by a digital comparator, if digital data exceeds a particular threshold, and 2) in response to the digital data determined to be above the threshold, transmitting, by the digital comparator, an output signal corresponding to the digital data to a digital-to-analog converter (DAC) device. Additionally, the DAC is configured to generate an analog signal.