Memory Array Circuitry Stability Enhancement via Voltage Control
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Solution Overview
Problem
Conventional techniques for ensuring memory cell stability in integrated circuits, such as adjusting transistor sizes and providing redundant resources, often result in undesirable overhead and do not effectively address memory cell reliability, particularly in programmable logic devices.
Innovation Solution
The implementation of precharging circuitry using n-channel metal-oxide-semiconductor transistors to reduce the precharge voltage and body bias adjustments for address transistors, which enhances memory cell stability by optimizing the threshold voltage and reducing the risk of read and write failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistor sizes are adjusted to ensure memory cell stability, then memory cell stability is improved, but device complexity and overhead increase
Solution Approach 1:
The patent changes the voltage parameter (precharge voltage level) to improve memory cell stability. By reducing the precharge voltage to be less than the core logic power supply voltage, the patent enhances stability without requiring physical changes to transistor sizes or adding redundant circuitry, thus avoiding increased device complexity.
2Reliability
If redundant resources are provided to repair defects, then reliability is improved, but device complexity and overhead increase
Solution Approach 1:
Instead of providing redundant circuitry, the patent uses parameter changes (voltage regulation and body bias adjustment) to achieve self-healing and stability enhancement. This approach improves reliability without adding redundant resources, thereby avoiding increased device complexity.
3Reliability
If precharge voltage is reduced to enhance memory cell stability, then memory cell stability is improved, but precharge effectiveness may be reduced
Solution Approach 1:
The patent optimizes the precharge voltage parameter to find the optimal balance between stability and effectiveness. By setting the precharge voltage to a specific level (less than core logic power supply voltage), the patent achieves both improved stability and maintained precharge effectiveness.
Solution Approach 2:
The patent uses programmable voltage regulation to dynamically adjust the precharge voltage based on operating conditions. This dynamic adjustment allows the system to optimize precharge effectiveness while maintaining stability enhancements across different operating scenarios.
4Reliability
If body bias adjustments are made to optimize threshold voltage, then memory cell stability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service through automated body bias optimization. During manufacturing, memory cells are tested to determine optimal body bias levels, and these settings are automatically stored in nonvolatile memory and applied during operation. This self-service approach improves stability without requiring complex manual adjustment mechanisms.
Solution Approach 2:
The patent performs body bias optimization in advance during manufacturing testing. By determining and storing optimal body bias settings before device deployment, the system eliminates the need for complex real-time adjustment circuitry, thereby improving stability without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves memory cell stability by reducing the precharge voltage and optimizing body bias settings, thereby enhancing the static noise margin and write margin, leading to more reliable memory operations in programmable logic devices.
Implementation Method 1
When n-channel metal-oxide-semiconductor transistors are used in the precharge drivers, the threshold voltage of the transistors reduces the magnitude of the voltage that is applied to the data lines
Implementation Method 2
By changing the body bias that is applied to the body bias terminals, the threshold voltage of the address transistors can be adjusted
Data Source
AI summary
Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays with memory cells arranged in rows and columns. Address lines may be associated with each row of memory cells and data lines may be associated with each column of memory cells. Precharge driver circuitry may be used to precharge the data lines to a precharge voltage prior to performing read operations. The integrated circuit may contain core logic that is powered using a core logic power supply voltage. The precharge voltage may be reduced with respect to the core logic power supply voltage. Each address transistor may have a body bias terminal. The integrated circuit may contain programmable voltage regulator circuitry that produces a body bias for the address transistors based on a body bias setting stored in nonvolatile memory on the integrated circuit.