Memory Array Data Storage Layout for In-Memory Logic
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Solution Overview
Problem
Existing memory systems require significant power and time to perform logical operations due to the need to transfer data between memory arrays and processing resources, and they often use a single storage layout for all data elements regardless of the operations to be performed, leading to inefficient use of compute components and increased power consumption.
Innovation Solution
The implementation of a memory system that organizes data elements in a particular storage layout based on the number of compute components, logical operations to be performed in parallel, and the type of operations, allowing for horizontal, vertical, or hybrid storage layouts, enabling more efficient use of compute components and reducing the need for data transfer via buses by performing logical operations within the memory array itself.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between memory arrays and processing resources via buses, then data can be accessed by functional units, but power consumption increases and time is lost during transfer
Solution Approach 1:
The patent merges the memory array and processing resources into a single integrated structure where compute components are embedded within the memory array. This allows data to be processed in-place without requiring transfer via external buses, thereby reducing power consumption and access time while maintaining full data accessibility.
Solution Approach 2:
The patent introduces local compute components as intermediaries within the memory array that can process data without requiring external processing resources. These embedded compute units act as intermediaries between storage and external processing, enabling operations to be performed closer to the data and reducing the need for high-power bus transfers.
2Device complexity
If a single storage layout is used for all data elements, then memory structure is simplified, but compute components are inefficiently utilized and power consumption increases
Solution Approach 1:
The patent implements dynamic storage layouts that can be reconfigured based on the specific computational task requirements. The memory array can adaptively change its organization pattern (e.g., row-major, column-major, or custom patterns) to optimize compute component utilization for different operations, thereby improving efficiency without significantly increasing structural complexity.
Solution Approach 2:
The patent changes the organizational parameters of the memory array based on computational needs. Different storage patterns (such as interleaved, blocked, or distributed layouts) can be selected to match the access patterns and computational requirements, optimizing the utilization of compute components while maintaining manageable structural complexity.
3Ease of operation
If data transfer via buses is required for logical operations, then processing can be performed externally, but time is lost during data movement
Solution Approach 1:
The patent extracts the processing function from external locations and embeds compute components directly within the memory array. This allows data to remain in place during processing operations, eliminating the time loss associated with transferring data to and from external processing units while maintaining full accessibility through the memory interface.
Data Source
AI summary
Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. The first address space is configured to store a logical representation of a first portion of a value. The example apparatus also comprising a second address space of the memory array comprising a second number of memory cells coupled to the plurality of sense lines and to a second select line. The second address space is configured to store a logical representation of a second portion of the value. The example apparatus also comprising sensing circuitry configured to receive the first value and perform a logical operation using the value without performing a sense line address access.