Memory Array Structure With Switch Segmentation For In-Memory Computing
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Solution Overview
Problem
Existing memory array structures for in-memory operations face challenges such as high power consumption, area inefficiency, and limited flexibility, particularly in handling sneak paths and supporting efficient multiply-accumulate operations for artificial intelligence applications.
Innovation Solution
A memory array structure is proposed, featuring a matrix of memory devices connected through switches, where each row has a row leading-out wire and each column has a column leading-out wire. The memory devices are connected to switches, allowing for independent control of each column, and the switches have a lower on-resistance than the parallel resistance of memory devices, enabling efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If switches are added to each intersection of the crossbar to solve sneak path leakage, then power consumption is reduced, but the area of the entire matrix increases
Solution Approach 1:
The invention segments the crossbar structure by introducing word lines that divide the memory array into multiple independently controllable banks. Each bank can be accessed separately, allowing the system to activate only the necessary portion of the array for a given operation, thereby reducing the effective area in use and minimizing sneak paths without requiring switches at every intersection.
Solution Approach 2:
The invention introduces word lines as intermediary elements between the row leading-out wires and the memory devices. These word lines act as mediators that enable selective activation of memory devices through controlled potential changes, eliminating the need for switches at each intersection while still preventing sneak path leakage through potential-based selection.
2Ease of operation
If an entire matrix or storage operation unit in the same row is opened during operation, then access to memory devices is simplified, but power consumption increases and flexibility is limited
Solution Approach 1:
The invention divides the memory array into multiple banks using word lines, where each bank corresponds to a specific row segment. This segmentation allows the system to open and access only the specific bank containing the target memory device, rather than opening the entire row or matrix. This selective bank access reduces the number of active memory devices, thereby lowering power consumption while maintaining ease of access to the required data.
Solution Approach 2:
The invention implements dynamic control of word line potentials to enable flexible and selective activation of different banks. By dynamically adjusting the potential of specific word lines, the system can adaptively activate only the necessary banks for the current operation, providing both ease of access and reduced power consumption through dynamic resource allocation.
3Ease of operation
If an entire matrix or storage operation unit in the same row is opened during operation, then memory device access is simplified, but operational flexibility is limited
Solution Approach 1:
The invention segments the memory array into multiple independently controllable banks using word lines. This segmentation enables the system to selectively access different banks based on the specific operation requirements, thereby enhancing operational flexibility. The segmented structure allows for fine-grained control over which memory devices are activated, supporting diverse access patterns and operational modes while maintaining ease of access to individual devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure allows for simultaneous output of analog currents for multiply-accumulate operations across different columns, significantly improving operation speed and efficiency while reducing power consumption and area requirements.
Implementation Method 1
the on-resistance of each of the switches is lower than the parallel resistance of all of the memory devices in the same column which are connected and in a low resistance state, and the off-resistance thereof is higher than the resistance of any one of the memory devices in the same column which are connected and in a high resistance state
Data Source
AI summary
The present invention disclosures a memory array structure, comprising an array composed of multiple memory devices arranged in rows and columns, each of the rows is set with a row leading-out wire, and each of the columns is set with a column leading-out wire, memory devices are correspondingly positioned at intersection points of each row leading-out wire and each column leading-out wire; wherein, the first terminal of each of the memory devices is individually connected to the row leading-out wire of the same row, and the second terminal of each of the memory devices is connected to a first terminal of a switch in the same column, the second terminal of the switch is connected to the column leading-out wire of the same column; wherein, each of the rows is set with one to multiple the switches, and the first terminal of each of the switches is connected to one to all of the second terminals of the memory devices in the same column. The advantage of the present invention is that the corresponding analog currents output of input signals of different specified rows according to multiply-accumulate operation requirements of each of the columns can be obtained simultaneously, thus multiply-accumulate operations of different input signals of different scales can be performed, which greatly improves operation speed and using efficiency of the array.