Memory Array Switches for Lower-Capacitance Global Routing
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Solution Overview
Problem
Existing memory systems face challenges in achieving area efficiency and operational speed due to high capacitive loading from numerous metal rails between the memory array and the memory controller.
Innovation Solution
Implementing switches to selectively couple or decouple local lines to global lines, reducing the number of global lines and minimizing capacitive loading, thereby improving operational speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If numerous metal rails are used to connect memory array to memory controller, then connectivity and access capability are improved, but capacitive loading increases and area efficiency deteriorates
Solution Approach 1:
The patent segments the metal rails into two hierarchical levels: global lines that span the entire memory array and local lines that serve specific blocks. Switches are introduced at block boundaries to selectively connect local lines to global lines. This segmentation reduces the total number of continuous metal rails needed, thereby reducing capacitive loading while maintaining connectivity through the switched network.
Solution Approach 2:
The patent introduces dynamically controllable switches that can selectively couple or decouple local lines to global lines based on operational requirements. This dynamic configuration allows the system to activate only the necessary connections during any given operation, reducing the effective capacitive loading compared to having all connections permanently active, while maintaining full adaptability when needed.
2Adaptability or versatility
If numerous metal rails are used to connect memory array to memory controller, then connectivity and access capability are improved, but area efficiency deteriorates
Solution Approach 1:
By segmenting the routing into global lines and local lines with switches at block boundaries, the patent reduces the number of long-spanning metal rails required. The global lines can be shared across multiple blocks, and local lines only need to extend to the nearest switch, thereby reducing overall routing area while maintaining full connectivity capability.
3Adaptability or versatility
If high capacitive loading is present from numerous metal rails, then comprehensive connectivity is achieved, but operational speed deteriorates
Solution Approach 1:
The dynamically controllable switches enable the system to activate only the necessary connections during any given operation, reducing the effective capacitive loading compared to having all connections permanently active. This dynamic configuration allows fast charging and discharge of capacitive loads by limiting the number of simultaneously active connections, thereby improving operational speed while maintaining full adaptability when needed.
Data Source
AI summary
Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.