Non-Volatile Memory Array for Analog Synapse Weight Computing

The patent merges the functions of synaptic weight storage and computation into a single non-volatile memory cell. The memory cell simultaneously stores weight values and performs analog multiplication with input signals during read operations, eliminating the need for separate CMOS analog computation circuits. This integration dramatically reduces circuit area while maintaining energy efficiency, as non-volatile memory cells require minimal power for read operations compared to active CMOS circuits.

The patent replaces digital mechanical/computational systems (CMOS logic circuits performing sequential multiplication and addition) with an analog physical system based on Ohm's law. Current flowing through memory cells representing synaptic weights naturally performs parallel multiplication with input voltages, and currents summing at node lines automatically perform addition. This physical analog computation achieves high computational parallelism with minimal energy consumption, as it leverages fundamental electrical properties rather than requiring complex digital processing.

The patent segments the control of the memory array into independent word lines and bit lines, allowing individual memory cells to be accessed by activating specific row and column selections. This segmentation enables precise individual programming and reading of synapse weights without disturbing other cells in the array. The segmented address decoding structure simplifies control logic compared to fully interconnected approaches, as each cell can be independently addressed through the intersection of selected word and bit lines.