Memory Array TAV Formation Using Metal Halide Silicon Reaction
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Solution Overview
Problem
Existing memory array fabrication methods face challenges in efficiently forming conductive interconnects through vertically-stacked memory cells, particularly in the formation of through-array vias (TAVs), which affect the electrical connectivity and reliability of memory cells.
Innovation Solution
A method involving 'gate-last' or 'replacement-gate' processing is employed to form memory arrays, where conductive vias are created by reacting silicon-containing materials with metal halides to deposit elemental metal, followed by forming conductive cores and linings, ensuring reliable electrical coupling of memory cells with the conductor tier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form through-array vias, then the manufacturing process is simpler, but the electrical connectivity and reliability of memory cells deteriorate
Solution Approach 1:
The method performs preliminary actions by forming the conductor tier with silicon-containing material before forming the through-array vias. This preliminary preparation enables subsequent chemical reactions (metal halide vapor phase deposition) to deposit high-purity metal directly into the vias, ensuring superior electrical connectivity is achieved through advance structural preparation rather than during the via formation itself.
Solution Approach 2:
The invention replaces conventional mechanical or physical via-filling methods with a chemical deposition process. Metal halide vapor phase deposition is used to chemically react and deposit elemental metal directly into the through-array vias, substituting traditional electroplating or electroless plating methods. This chemical approach enables more controlled, uniform, and high-purity metal deposition, significantly improving electrical conductivity and reliability.
2Reliability
If conventional via formation methods are used, then the manufacturing process is faster, but the conductivity of interconnects deteriorates
Solution Approach 1:
The invention changes the fundamental parameter of metal deposition by using metal halide vapor phase deposition instead of conventional plating methods. This parameter change enables direct chemical reaction and deposition of high-purity metal with superior conductivity. The process controls deposition through temperature, pressure, and vapor flow parameters, achieving optimal conductivity while maintaining reasonable fabrication throughput.
Solution Approach 2:
The through-array vias are formed as composite structures with multiple layers: a conductor tier base of silicon-containing material, intermediate metal layers deposited via chemical vapor deposition, and potentially additional conductive materials. This composite structure combines the advantages of different materials to achieve superior overall conductivity and reliability that cannot be obtained with single-material conventional via formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical connectivity and reliability of memory cells by creating conductive vias with higher conductivity materials, improving the overall performance and stability of the memory array.
Implementation Method 1
A metal halide is reacted with the silicon of the silicon-containing material to deposit the metal of the metal halide in the conductor tier
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier that comprises silicon-containing material. The stack comprises laterally-spaced memory-block regions and a through-array-via (TAV) region. The stack comprises channel-material strings that extend through the first tiers and the second tiers in the memory-block regions. The stack comprises TAV openings in the TAV region that extend to the silicon-containing material of the conductor tier. A metal halide is reacted with the silicon of the silicon-containing material to deposit the metal of the metal halide in the conductor tier. After depositing the metal, conductive material is formed in the TAV openings directly against the deposited metal and therefrom a TAV is formed in individual of the TAV openings that comprises the conductive material and the deposited metal. Structure embodiments are disclosed.