3D Memory Array Strings With TAV Interconnect and Insulator Walls

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Solution Overview

Problem

Existing memory array fabrication methods face challenges in efficiently forming strings of memory cells with reliable electrical connections and structural integrity, particularly in vertically-stacked configurations, which can affect data retention and access performance.

Innovation Solution

A method involving 'gate-last' or 'replacement-gate' processing is employed to form memory arrays, utilizing insulator walls and through-array vias to create stable electrical connections between memory cells, with channel material strings and conductor tiers, ensuring robust interconnectivity and data storage capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication methods are used to form vertically-stacked memory cells, then manufacturing process simplicity is maintained, but electrical connection reliability and structural integrity deteriorate

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidfabrication process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The method performs preliminary actions by forming insulator walls and through-array vias before forming the stack of memory cells. This preliminary preparation ensures that electrical connection pathways are established in advance, improving reliability without compromising manufacturability when integrated into the overall fabrication sequence.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The fabrication process is segmented into distinct stages: forming insulator walls, creating through-array vias, forming the stack, and establishing electrical connections. This segmentation allows each component to be optimized independently while maintaining overall process feasibility.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If vertically-stacked memory cell structures are implemented, then memory density is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvememory cell densityVSAvoidalignment precision

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

Insulator walls and through-array vias are formed as preliminary structures before stacking memory cells. These pre-formed structures serve as alignment references and structural guides, reducing the precision requirements for subsequent stacking operations while enabling high-density vertical configurations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Insulator walls act as intermediary structures between the substrate and the stack of memory cells. These intermediaries provide mechanical support and electrical isolation, facilitating precise positioning and reducing alignment tolerances required for high-density vertical stacking.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If through-array vias and insulator walls are formed, then electrical connectivity is enhanced, but device complexity increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The through-array vias serve multiple functions: they provide electrical connections, act as alignment references, and serve as structural supports. The insulator walls simultaneously provide electrical isolation, mechanical support, and define the boundaries of memory blocks. This multi-functionality reduces the need for additional specialized structures.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The method merges the formation of insulator walls and through-array vias into a coordinated process sequence that occurs before stack formation. This integration allows both structures to work together synergistically, enhancing electrical connectivity without proportionally increasing complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20260082888A1Memory Arrays Comprising Strings of Memory Cells and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells

Publication Date: 2026.03.19 MICRON TECHNOLOGY INC

AI summary

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. The conductor tier is directly above a lower tier that comprises conductive lines that are horizontally elongated. An insulator tier is vertically between the conductor tier and the lower tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to the conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually directly electrically couple to one of the conductive lines. Insulator walls are in the TAV region. The insulator walls extend vertically through the conductor tier and the insulator tier to the lower tier and are horizontally elongated. Methods are also disclosed.