3D Memory Array TAV Layout for Reliable Cell-String Connectivity

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current memory array technologies face challenges in efficiently forming strings of memory cells with optimal electrical connectivity and structural integrity, particularly in the formation of through-array vias and memory blocks, which affects the overall performance and reliability of memory arrays.

Innovation Solution

The method involves forming a stack with alternating conductive and insulative tiers, where partially-sacrificial plugs and insulative rings are used to create channel-material strings that extend through the tiers, and through-array vias are formed to connect these strings, ensuring direct electrical coupling with the conductor tier and lateral isolation between memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional memory array formation methods are used, then manufacturing process is simpler, but electrical connectivity and structural integrity are compromised

Engineering Contradiction:

Improvestructural integrityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The memory array is divided into multiple strings of memory cells, with each string forming an independent vertical structure. This segmentation allows for improved structural integrity of individual strings while maintaining overall array functionality, and enables modular manufacturing approaches that can simplify the overall fabrication process despite the increased structural complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar memory cell arrangements to vertically-stacked three-dimensional structures. By forming memory cells in multiple tiers stacked vertically, the invention achieves better electrical connectivity and structural integrity through the vertical dimension, while also increasing storage density without expanding the lateral footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If vertically-stacked memory cells are formed, then storage density increases, but formation of through-array vias becomes more difficult

Engineering Contradiction:

Improvestorage densityVSAvoidvia formation difficulty

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

Sacrificial plugs are formed in advance during the stack fabrication process, positioned at locations where through-array vias will eventually be created. These preliminary sacrificial structures guide the subsequent via formation process, enabling precise via placement in the complex vertical stack without requiring difficult post-fabrication alignment procedures.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Sacrificial plugs serve as intermediary structures during manufacturing. These temporary elements facilitate the formation of through-array vias by providing defined etch pathways through the vertical stack, and are subsequently removed to create the final via structures. This intermediary approach simplifies via formation in three-dimensional stacked architectures.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If through-array vias are formed to connect memory cell strings, then electrical connectivity improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improveelectrical connectivityVSAvoidvia alignment precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

Sacrificial plugs are formed at predetermined locations during the stack fabrication process, establishing precise via positions before the actual via formation occurs. This preliminary positioning ensures accurate alignment of through-array vias with underlying and overlying conductive structures, meeting stringent manufacturing precision requirements through built-in guidance features rather than relying solely on high-precision alignment processes.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12176034B2Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Publication Date: 2024.12.24 MICRON TECHNOLOGY INC

AI summary

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through a lowest of the conductive tiers. Insulative rings are in the lowest conductive tier in the TAV region. Individual of the insulative rings encircle individual of the TAVs. The insulative rings extend through the lowest conductive tier and into the conductor tier. Outer rings are in the lowest conductive tier that individually encircle one of the individual insulative rings that encircle the individual TAVs. Other embodiments, including method, are disclosed.