3D Memory Array TAV Formation With Shared Trench Metallization
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Solution Overview
Problem
Current memory array fabrication methods face challenges in efficiently forming strings of memory cells with optimal electrical connectivity and structural integrity, particularly in the formation of through-array-vias and conductive lines, which can lead to increased manufacturing time and costs.
Innovation Solution
The method involves forming a stack with vertically-alternating conductive and insulative tiers, where channel-material strings extend through both, and through-array-via constructions with conductive cores and non-conductive cylinders are created, allowing for direct electrical coupling to a conductor tier, with specific etching and material deposition processes to form conductive lines and memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication methods are used to form through-array-vias and conductive lines, then structural integrity is achieved, but manufacturing time and costs increase
Solution Approach 1:
The patent combines the formation of through-array-vias and conductive lines into a single integrated fabrication process. The conductive lines are formed by extending conductive material from the through-array-via regions through the memory array, eliminating the need for separate via formation and line formation steps. This merging of processes directly reduces manufacturing time while maintaining structural integrity.
Solution Approach 2:
The method performs preliminary actions by forming the through-array-via constructions with conductive cores and non-conductive cylinders before completing the conductive line formation. The via regions are prepared in advance with the conductive material already in place, allowing subsequent conductive lines to be formed by simple extension rather than requiring separate via drilling and filling operations.
2Ease of manufacture
If conventional fabrication methods are used to form strings of memory cells, then structural integrity is achieved, but manufacturing costs increase
Solution Approach 1:
The patent merges multiple fabrication operations into unified process steps. The formation of through-array-vias, conductive lines, and memory cell strings is achieved through combined deposition and etching processes rather than sequential separate operations. This reduces the total number of fabrication steps, lowering manufacturing costs while managing device complexity.
Solution Approach 2:
The conductive material deposition process serves multiple functions simultaneously: it forms the conductive cores of through-array-vias, creates the conductive lines that interconnect memory cells, and establishes electrical connections to conductor tiers. This multi-functionality reduces the need for specialized process steps for each feature, simplifying the overall fabrication process and reducing costs.
3Reliability
If direct electrical coupling to conductor tier is implemented, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The through-array-via constructions are formed in advance with precise positioning relative to the conductor tier. The conductive cores are deposited within non-conductive cylinders that are pre-positioned to ensure proper alignment. This preliminary formation of via structures with built-in alignment features reduces the precision requirements for subsequent conductive line formation steps.
Solution Approach 2:
The non-conductive cylinders serve as intermediary structures that facilitate precise electrical coupling. These cylinders provide physical boundaries and alignment references that guide the formation of conductive material, ensuring accurate positioning of through-array-vias relative to conductor tiers without requiring ultra-precise direct alignment operations.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions and a through-array-via (TAV) region. The stack comprises channel-material strings extending through the first tiers and the second tiers. The stack comprises horizontally-elongated trenches extending through the first tiers and the second tiers and that are individually between immediately-laterally-adjacent of the memory-block regions. The stack comprises TAV openings in the TAV region. Conductive material is formed in the TAV openings and in the horizontally-elongated trenches at the same time. All of the conductive material is removed from the horizontally-elongated trenches while leaving the conductive material in the TAV openings to comprise TAVs therein in a finished circuitry construction. After the removing, intervening material is formed in the horizontally-elongated trenches. Other embodiments, including structure, are disclosed.