Memory Array TAV Insulator Walls for Reliable Cell Coupling
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Solution Overview
Problem
Existing memory array fabrication methods face challenges in efficiently forming through-array-via regions and insulator walls, which affect the electrical connectivity and reliability of memory cells.
Innovation Solution
A method involving the formation of insulator walls through the conductor and insulator tiers, followed by the construction of vertically alternating conductive and insulative tiers, and the creation of channel material strings and through-array-vias to enhance electrical coupling between memory cells and control circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form through-array-via regions and insulator walls, then the fabrication process is simpler, but the electrical connectivity and reliability of memory cells deteriorate
Solution Approach 1:
The method performs preliminary actions by forming insulator walls in the through-array-via region before forming the memory cell strings. This sequential approach ensures that the via regions are properly isolated and electrically defined before the complex memory structures are built, improving reliability without requiring a complete redesign of the fabrication process
Solution Approach 2:
The fabrication process is segmented into distinct stages: first forming insulator walls in TAV regions, then forming memory cell strings in separate regions. This segmentation allows each structure to be optimized independently, with insulator walls providing electrical isolation and memory strings providing storage functionality, thereby improving overall electrical connectivity and reliability
2Reliability
If insulator walls are formed extending through conductor and insulator tiers, then electrical isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The formation of insulator walls is merged with the existing tier structure of the memory array. The insulator walls extend through conductor and insulator tiers, utilizing the existing layered architecture to provide electrical isolation. This approach integrates the isolation function into the existing manufacturing flow rather than adding a completely separate process
Solution Approach 2:
Insulator walls are formed specifically in the through-array-via regions where electrical isolation is most critical. This localized approach provides enhanced electrical isolation precisely where needed (at the via regions connecting to control circuitry) without requiring insulator walls throughout the entire structure, balancing manufacturing ease with reliability
Data Source
AI summary
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. The conductor tier is directly above a lower tier that comprises conductive lines that are horizontally elongated. An insulator tier is vertically between the conductor tier and the lower tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to the conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually directly electrically couple to one of the conductive lines. Insulator walls are in the TAV region. The insulator walls extend vertically through the conductor tier and the insulator tier to the lower tier and are horizontally elongated. Methods are also disclosed.