3D Memory Array Decoding With TFT Interconnects for Higher Density
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Solution Overview
Problem
The challenge in memory devices is to increase memory cell density while minimizing the size of complementary metal oxide semiconductor (CMOS) circuitry, which expands with the number of decks in three-dimensional (3D) memory devices, leading to increased costs and power consumption.
Innovation Solution
The use of thin film transistors (TFTs) within array layers to select or inhibit decks of memory cells, reducing the need for larger CMOS circuitry and allowing for more decks without increasing substrate area, along with flexible fabrication techniques to optimize processing conditions and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of decks in three-dimensional memory devices is increased to increase memory cell density, then memory cell density is improved, but the size of CMOS circuitry increases leading to increased costs and power consumption
Solution Approach 1:
The patent extracts the decoding function from the CMOS circuitry and relocates it to the array layers using TFT-based decoders. This separation removes the burden from CMOS circuitry, allowing it to remain compact while still supporting increased memory cell density through the embedded TFT decoders in the array layers.
Solution Approach 2:
The patent moves the decoding functionality from the traditional planar CMOS layer to the vertical array layers structure. By implementing decoders within the array layers themselves using TFTs, the system adds a dimensional aspect to the decoding architecture, allowing parallel decoding operations that scale with memory density without increasing CMOS footprint.
2Quantity of substance
If the number of decks in three-dimensional memory devices is increased to increase memory cell density, then memory cell density is improved, but power consumption increases
Solution Approach 1:
The patent extracts the power-intensive decoding operations from the CMOS circuitry and places them in the array layers using TFT-based decoders. This distribution of computational workload reduces the power burden on the CMOS circuitry, enabling higher memory cell density without proportional increases in overall power consumption.
Solution Approach 2:
The array layers perform their own decoding operations using embedded TFT decoders, making the system self-sufficient in terms of address decoding. This self-service capability at the array layer level eliminates the need for extensive CMOS-based decoding circuitry, thereby reducing overall power consumption while supporting increased memory density.
3Device complexity
If thin film transistors are used within array layers to select decks, then the need for larger CMOS circuitry is reduced, but fabrication complexity increases
Solution Approach 1:
The patent merges the decoder functionality with the array layer structure by integrating TFT-based decoders directly into the array layers. This consolidation eliminates the need for separate, large CMOS decoder circuits and allows the use of existing TFT fabrication processes, thereby reducing CMOS circuitry size while managing fabrication complexity through process integration.
Solution Approach 2:
The TFT structures serve multiple functions: they act as both memory cell components and decoder elements within the array layers. This multi-functionality reduces the need for dedicated CMOS decoder circuitry, shrinking the CMOS footprint while the TFT fabrication processes remain compatible with standard semiconductor manufacturing techniques.
Data Source
AI summary
Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.